High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX
Datasheet
6.1.2
Special Restrictions on Back-to-Back Read Cycles
There are also restrictions on specific back-to-back read operations. These restrictions concern
reading specific registers after reading resources that have side effects. In many cases there is a delay
between reading the LAN9218, and the subsequent indication of the expected change in the control
register values.
In order to prevent the host from reading stale data on back-to-back reads, minimum wait periods have
been established. These periods are specified in Table 6.2, "Read After Read Timing Rules". The host
processor is required to wait the specified period of time between read operations of specific
combinations of resources. The wait period is dependant upon the combination of registers being read.
Performing "dummy" reads of the BYTE_TEST register is a convenient way to guarantee that the
minimum wait time restriction is met. Table 6.2 also shows the number of dummy reads that are
required for back-to-back read operations. The number of BYTE_TEST reads in this table is based on
the minimum timing for Tcycle (45ns). For microprocessors with slower busses the number of reads
may be reduced as long as the total time is equal to, or greater than the time specified in the table.
Dummy reads of the BYTE_TEST register are not required as long as the minimum time period is met.
Table 6.2 Read After Read Timing Rules
OR PERFORM THIS MANY
READS OF BYTE_TEST…
(ASSUMING Tcycle OF 45NS)
AFTER
READING...
WAIT FOR THIS MANY
NS…
BEFORE READING...
RX Data FIFO
RX Status FIFO
TX Status FIFO
RX_DROP
135
135
135
180
3
3
3
4
RX_FIFO_INF
RX_FIFO_INF
TX_FIFO_INF
RX_DROP
SMSC LAN9218
115
Revision 1.5 (07-18-06)
DATASHEET
SMSC [ SMSC CORPORATION ]
