16-bit High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX
Datasheet
Table 2.5 System and Power Signals (continued)
PIN
NO.
BUFFER
TYPE
NUM
PINS
NAME
SYMBOL
DESCRIPTION
Ground for I/O pins
19,27,
34,41,
47,54,
60,96
I/O Ground
GND_IO
P
8
81,85,
89
+3.3V Analog
Power
VDD_A
VSS_A
P
P
P
3
4
2
+3.3V analog power supply pins. See
Note 2.1.
77,80,
86,88
Analog Ground
Ground for analog circuitry
3,65
Core Voltage
Decoupling
VDD_CORE
+1.8 V from internal core regulator.
Both pins must be connected
together externally. Each pin requires
a 0.01uF decoupling capacitor. In
addition, pin 3 requires a bulk 10uF
capacitor (<2 Ohm ESR) in parallel.
See Note 2.1.
1,66
7
Core Ground
PLL Power
GND_CORE
VDD_PLL
P
P
2
1
Ground for internal digital logic
+1.8V Power from the internal PLL
regulator. This pin must be connected
to a 10uF capacitor (<2 Ohm ESR), in
parallel with a 0.01uF capacitor to
ground. See Note 2.1.
4
8
PLL Ground
VSS_PLL
VDD_REF
P
P
1
1
GND for the PLL
Reference Power
Connected to 3.3v power and used
as the reference voltage for the
internal PLL
11
Reference Ground
VSS_REF
P
1
Ground for internal PLL reference
voltage
Note 2.1 Please refer to the SMSC application note AN15.5 - “Migrating from LAN9117 to the
LAN9217” for additional details.
SMSC LAN9217
19
Revision 1.8 (06-06-07)
DATASHEET
SMSC [ SMSC CORPORATION ]
