16-bit High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX
Datasheet
Table 2.1 Host Bus Interface Signals
BUFFER
TYPE
#
PIN NO.
NAME
SYMBOL
PINS
DESCRIPTION
Bi-directional data port.
43-46,49-
53,56-59,62-
64
Host Data
D[15:0]
I/O8
16
12-18
92
Host Address
Read Strobe
Write Strobe
A[7:1]
nRD
IS
IS
IS
7
1
1
7-bit Address Port. Used to select
Internal CSR’s and TX and RX FIFOs.
Active low strobe to indicate a read
cycle.
93
nWR
Active low strobe to indicate a write
cycle. This signal, qualified with nCS, is
also used to wakeup the LAN9217
when it is in a reduced power state.
94
Chip Select
nCS
IS
1
Active low signal used to qualify read
and write operations. This signal
qualified with nWR is also used to
wakeup the LAN9217 when it is in a
reduced power state.
72
76
Interrupt
Request
IRQ
O8/OD8
IS
1
1
Programmable Interrupt request.
Programmable polarity, source and
buffer types.
FIFO Select
FIFO_SEL
When driven high all accesses to the
LAN9217 are to the RX or TX Data
FIFOs. In this mode, the A[7:3] upper
address inputs are ignored.
Table 2.2 Default Ethernet Settings
DEFAULT ETHERNET SETTINGS
DUPLEX
SPEED_SEL
SPEED
AUTO NEG.
0
1
10Mbps
Half-Duplex
Half-Duplex
Disabled
Enabled
100Mbps
SMSC LAN9217
15
Revision 1.8 (06-06-07)
DATASHEET
SMSC [ SMSC CORPORATION ]
