16-bit High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX
Datasheet
Table 2.5 System and Power Signals (continued)
PIN
NO.
BUFFER
TYPE
NUM
PINS
NAME
SYMBOL
DESCRIPTION
74
10/100 Selector
SPEED_SEL
I
1
This signal functions as a
configuration input on power-up and
is used to select the default Ethernet
settings. Upon deassertion of reset,
the value of the input is latched. This
signal functions as shown in
Table 2.2, "Default Ethernet Settings",
below.
(PU)
71,84,
90,91
No Connect
NC
4
3
No Connect. These pins must be left
open.
100,
99,98
General Purpose
I/O data,
nLED1 (Speed
GPIO[2:0]/
nLED[3:1]
IS/O12/
OD12
General Purpose I/O data: These
three general-purpose signals are
fully programmable as either push-
pull output, open-drain output or input
by writing the GPIO_CFG
configuration register in the CSR’s.
They are also multiplexed as GP LED
connections.
Indicator),
nLED2 (Link &
Activity Indicator),
nLED3 (Full-
Duplex
GPIO signals are Schmitt-triggered
inputs. When configured as LED
outputs these signals are open-drain.
Indicator).
nLED1 (Speed Indicator). This
signal is driven low when the
operating speed is 100Mbs, during
auto-negotiation and when the cable
is disconnected. This signal is driven
high only during 10Mbs operation.
nLED2 (Link & Activity Indicator).
This signal is driven low (LED on)
when the LAN9217 detects a valid
link. This signal is pulsed high (LED
off) for 80mS whenever transmit or
receive activity is detected. This
signal is then driven low again for a
minimum of 80mS, after which time it
will repeat the process if TX or RX
activity is detected. Effectively, LED2
is activated solid for a link. When
transmit or receive activity is sensed
LED2 will flash as an activity
indicator.
nLED3 (Full-Duplex Indicator). This
signal is driven low when the link is
operating in full-duplex mode.
PLL Bias: Connect to an external
12.0K ohm 1.0% resistor to ground.
Used for the PLL Bias circuit.
10
RBIAS
RBIAS
AI
1
This pin must be connected to VDD
for normal operation.
9
2
Test Pin
ATEST
VREG
I
1
1
Internal Regulator
Power
P
3.3V input for internal voltage
regulator
20,28,
35,
+3.3V I/O Power
VDD_IO
P
8
+3.3V I/O logic power supply pins
42,48,
55,61,
97
Revision 1.8 (06-06-07)
18
SMSC LAN9217
DATASHEET
SMSC [ SMSC CORPORATION ]
