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LAN9215I-MT 参数 Datasheet PDF下载

LAN9215I-MT图片预览
型号: LAN9215I-MT
PDF下载: 下载PDF文件 查看货源
内容描述: 高效的单芯片10/100以太网控制器与HP Auto-MDIX的和工业温度支持 [Highly Efficient Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support]
分类和应用: 外围集成电路数据传输控制器局域网以太网局域网(LAN)标准时钟
文件页数/大小: 134 页 / 1602 K
品牌: SMSC [ SMSC CORPORATION ]
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Highly Efficient Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support  
Datasheet  
Note: An RX Data FIFO Direct PIO Burst Read cycle begins when both nCS and nRD are asserted.  
The cycle ends when either or both nCS and nRD are deasserted. They may be asserted and  
deasserted in any order.  
6.6  
PIO Writes  
PIO writes are used for all LAN9215I write cycles. PIO writes can be performed using Chip Select  
(nCS) or Write Enable (nWR). Either or both of these control signals must go high between cycles for  
the period specified.  
A[7:1]  
nCS, nRD  
Data Bus  
Figure 6.5 PIO Write Cycle Timing  
Note: The “Data Bus” width is 16 bits.  
Table 6.7 PIO Write Cycle Timing  
SYMBOL  
DESCRIPTION  
MIN  
TYP  
MAX  
UNITS  
tcycle  
tcsl  
Write Cycle Time  
165  
32  
13  
0
ns  
ns  
ns  
ns  
ns  
ns  
ns  
nCS, nWR Assertion Time  
nCS, nWR Deassertion Time (see Note below)  
Address Setup to nCS, nWR Assertion  
Address Hold Time  
tcsh  
tasu  
tah  
133  
0
tdsu  
tdh  
Data Setup to nCS, nWR Deassertion  
Data Hold Time  
7
0
Note: A PIO Write cycle begins when both nCS and nWR are asserted. The cycle ends when either  
or both nCS and nWR are deasserted. They may be asserted and deasserted in any order.  
Parameters tcsh and tcsl must be extended using wait states to meet the tcycle minimum.  
SMSC LAN9215I  
125  
Revision 1.5 (07-18-06)  
DATASHEET  
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