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LAN9215I-MT 参数 Datasheet PDF下载

LAN9215I-MT图片预览
型号: LAN9215I-MT
PDF下载: 下载PDF文件 查看货源
内容描述: 高效的单芯片10/100以太网控制器与HP Auto-MDIX的和工业温度支持 [Highly Efficient Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support]
分类和应用: 外围集成电路数据传输控制器局域网以太网局域网(LAN)标准时钟
文件页数/大小: 134 页 / 1602 K
品牌: SMSC [ SMSC CORPORATION ]
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Highly Efficient Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support  
Datasheet  
6.5  
RX Data FIFO Direct PIO Burst Reads  
In this mode the upper address inputs are not decoded, and any burst read of the LAN9215I will read  
the RX Data FIFO. This mode is enabled when FIFO_SEL is driven high during a read access. This  
is normally accomplished by connecting the FIFO_SEL signal to a high-order address line. This mode  
is useful when the host processor must increment its address when accessing the LAN9215I. Timing  
is identical to a PIO Burst Read, and the FIFO_SEL signal has the same timing characteristics as the  
address lines.  
In this mode, performance is improved by allowing an unlimited number of back-to-back DWORD or  
WORD read cycles. RX Data FIFO Direct PIO Burst Reads can be performed using Chip Select (nCS)  
or Read Enable (nRD). When either or both of these control signals go high, they must remain high  
for the period specified.  
Note that address lines A[2:1] are still used, and address bits A[7:3] are ignored.  
FIFO_SEL  
A[2:1]  
nCS, nRD  
Data Bus  
Figure 6.4 RX Data FIFO Direct PIO Burst Read Cycle Timing  
Note: The “Data Bus” width is 16 bits.  
Table 6.6 RX Data FIFO Direct PIO Burst Read Cycle Timing  
SYMBOL  
DESCRIPTION  
MIN  
TYP  
MAX  
UNITS  
tcsh  
tcsdv  
tacyc  
tasu  
tadv  
tah  
nCS, nRD Deassertion Time  
nCS, nRD Valid to Data Valid  
Address Cycle Time  
13  
ns  
ns  
30  
165  
0
Address, FIFO_SEL Setup to nCS, nRD Valid  
Address Stable to Data Valid  
Address, FIFO_SEL Hold Time  
Data Buffer Turn On Time  
ns  
40  
7
0
0
ns  
ns  
ns  
ns  
tdon  
tdoff  
tdoh  
Data Buffer Turn Off Time  
Data Output Hold Time  
0
Revision 1.5 (07-18-06)  
124  
SMSC LAN9215I  
DATASHEET  
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