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LAN9215I-MT 参数 Datasheet PDF下载

LAN9215I-MT图片预览
型号: LAN9215I-MT
PDF下载: 下载PDF文件 查看货源
内容描述: 高效的单芯片10/100以太网控制器与HP Auto-MDIX的和工业温度支持 [Highly Efficient Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support]
分类和应用: 外围集成电路数据传输控制器局域网以太网局域网(LAN)标准时钟
文件页数/大小: 134 页 / 1602 K
品牌: SMSC [ SMSC CORPORATION ]
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Highly Efficient Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support  
Datasheet  
6.2  
PIO Reads  
PIO reads can be used to access CSRs or RX Data and RX/TX status FIFOs. In this mode, counters  
in the CSRs are latched at the beginning of the read cycle. Read data is valid as indicated in the timing  
diagram. PIO reads can be performed using Chip Select (nCS) or Read Enable (nRD). Either or both  
of these control signals must go high between cycles for the period specified.  
Note: Some registers have restrictions on the timing of back-to-back, write-read and read-read  
cycles.  
A[7:1]  
nCS, nRD  
Data Bus  
Figure 6.1 PIO Read Cycle Timing  
Note: The “Data Bus” width is 16 bits  
Table 6.3 PIO Read Timing  
SYMBOL  
DESCRIPTION  
MIN  
TYP  
MAX  
UNITS  
tcycle  
tcsl  
Read Cycle Time  
165  
32  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
nCS, nRD Assertion Time  
tcsh  
tcsdv  
tasu  
tah  
nCS, nRD Deassertion Time (see Note below)  
nCS, nRD Valid to Data Valid  
Address Setup to nCS, nRD Valid  
Address Hold Time  
13  
133  
30  
0
0
0
tdon  
tdoff  
tdoh  
Data Buffer Turn On Time  
Data Buffer Turn Off Time  
7
Data Output Hold Time  
0
Note: A PIO Read cycle begins when both nCS and nRD are asserted. The cycle ends when either  
or both nCS and nRD are deasserted. They may be asserted and deasserted in any order.  
Parameters tcsh and tcsl must be extended using wait states to meet the tcycle minimum.  
SMSC LAN9215I  
121  
Revision 1.5 (07-18-06)  
DATASHEET  
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