Highly Efficient Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support
Datasheet
6.2
PIO Reads
PIO reads can be used to access CSRs or RX Data and RX/TX status FIFOs. In this mode, counters
in the CSRs are latched at the beginning of the read cycle. Read data is valid as indicated in the timing
diagram. PIO reads can be performed using Chip Select (nCS) or Read Enable (nRD). Either or both
of these control signals must go high between cycles for the period specified.
Note: Some registers have restrictions on the timing of back-to-back, write-read and read-read
cycles.
A[7:1]
nCS, nRD
Data Bus
Figure 6.1 PIO Read Cycle Timing
Note: The “Data Bus” width is 16 bits
Table 6.3 PIO Read Timing
SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNITS
tcycle
tcsl
Read Cycle Time
165
32
ns
ns
ns
ns
ns
ns
ns
ns
ns
nCS, nRD Assertion Time
tcsh
tcsdv
tasu
tah
nCS, nRD Deassertion Time (see Note below)
nCS, nRD Valid to Data Valid
Address Setup to nCS, nRD Valid
Address Hold Time
13
133
30
0
0
0
tdon
tdoff
tdoh
Data Buffer Turn On Time
Data Buffer Turn Off Time
7
Data Output Hold Time
0
Note: A PIO Read cycle begins when both nCS and nRD are asserted. The cycle ends when either
or both nCS and nRD are deasserted. They may be asserted and deasserted in any order.
Parameters tcsh and tcsl must be extended using wait states to meet the tcycle minimum.
SMSC LAN9215I
121
Revision 1.5 (07-18-06)
DATASHEET
SMSC [ SMSC CORPORATION ]
