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LAN9215I-MT 参数 Datasheet PDF下载

LAN9215I-MT图片预览
型号: LAN9215I-MT
PDF下载: 下载PDF文件 查看货源
内容描述: 高效的单芯片10/100以太网控制器与HP Auto-MDIX的和工业温度支持 [Highly Efficient Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support]
分类和应用: 外围集成电路数据传输控制器局域网以太网局域网(LAN)标准时钟
文件页数/大小: 134 页 / 1602 K
品牌: SMSC [ SMSC CORPORATION ]
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Highly Efficient Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support  
Datasheet  
Chapter 6 Timing Diagrams  
6.1  
Host Interface Timing  
The LAN9215I supports the following host cycles:  
Read Cycles:  
„
„
„
„
PIO Reads (nCS or nRD controlled)  
PIO Burst Reads (nCS or nRD controlled)  
RX Data FIFO Direct PIO Reads (nCS or nRD controlled)  
RX Data FIFO Direct PIO Burst Reads (nCS or nRD controlled)  
Write Cycles:  
„
„
PIO writes (nCS and nWR controlled)  
TX Data FIFO direct PIO writes (nCS or nWR controlled)  
6.1.1  
Special Restrictions on Back-to-Back Write/Read Cycles  
It is important to note that there are specific restrictions on the timing of back-to-back write-read  
operations. These restrictions concern reading the control registers after any write cycle to the  
LAN9215I device. In many cases there is a required minimum delay between writing to the LAN9215I,  
and the subsequent side effect (change in the control register value). For example, when writing to the  
TX Data FIFO, it takes up to 135ns for the level indication to change in the TX_FIFO_INF register.  
In order to prevent the host from reading stale data after a write operation, minimum wait periods must  
be enforced. These periods are specified in Table 6.1, "Read After Write Timing Rules". The host  
processor is required to wait the specified period of time after any write to the LAN9215I before reading  
the resource specified in the table. These wait periods are for read operations that immediately follow  
any write cycle. Note that the required wait period is dependant upon the register being read after the  
write.  
Performing "dummy" reads of the BYTE_TEST register is a convenient way to guarantee that the  
minimum write-to-read timing restriction is met. Table 6.1 also shows the number of dummy reads that  
are required before reading the register indicated. The number of BYTE_TEST reads in this table is  
based on the minimum timing for Tcycle (165ns). For microprocessors with slower busses the number  
of reads may be reduced as long as the total time is equal to, or greater than the time specified in the  
table. Note that dummy reads of the BYTE_TEST register are not required as long as the minimum  
time period is met.  
Table 6.1 Read After Write Timing Rules  
MINIMUM WAIT TIME FOR READ  
FOLLOWING ANY WRITE CYCLE  
(IN NS)  
NUMBER OF BYTE_TEST  
READS  
(ASSUMING TCYCLE OF 165NS)  
REGISTER NAME  
ID_REV  
IRQ_CFG  
INT_STS  
INT_EN  
0
0
3
2
1
0
1
495  
330  
165  
0
BYTE_TEST  
FIFO_INT  
165  
Revision 1.5 (07-18-06)  
118  
SMSC LAN9215I  
DATASHEET  
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