High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
Datasheet
14.5.4.27 Buffer Manager Interrupt Pending Register (BM_IPR)
Register #:
1C21h
Size:
32 bits
This register contains the Buffer Manager interrupt status. The status is double buffered. All interrupts
in this register may be masked via the Buffer Manager Interrupt Mask Register (BM_IMR) register.
Refer to Chapter 5, "System Interrupts," on page 49 for more information.
BITS
DESCRIPTION
TYPE
DEFAULT
31:14
13:10
RESERVED
RO
RC
-
Drop Reason B
0h
When bit 7 is set, these bits indicate the reason a packet was dropped per
the table below:
BIT
VALUES
DESCRIPTION
0000
The destination address was not in the ALR table (unknown or broadcast), and
the Broadcast Buffer Level was exceeded.
0001
0010
0011
0100
Drop on Red was set and the packet was colored Red.
There were no buffers available.
There were no memory descriptors available.
The destination address was not in the ALR table (unknown or broadcast) and
there were no valid destination ports.
0101
0110
0111
1000
1001
The packet had a receive error and was >64 bytes
The Buffer Drop Level was exceeded.
RESERVED
RESERVED
Drop on Yellow was set, the packet was colored Yellow and was randomly
selected to be dropped.
1010
1011
1100
1101
1110
1111
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
9:8
Source Port B
RC
RC
00b
When bit 7 is set, these bits indicate the source port on which the packet
was dropped.
00 = Port 0
01 = Port 1
10 = Port 2
11 = RESERVED
7
Status B Pending
When set, bits 13:8 are valid.
0b
SMSC LAN9312
439
Revision 1.2 (04-08-08)
DATASHEET
SMSC [ SMSC CORPORATION ]
