High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
Datasheet
Table 10.5 Microwire Command Set for 9 Address Bits (continued)
START
BIT
DATA TO
EEPROM
DATA FROM
EEPROM
# OF
CLOCKS
INST
OPCODE
ADDRESS
EWDS
EWEN
READ
WRITE
WRAL
1
1
1
1
1
00
00
10
01
00
0
1
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
-
Hi-Z
Hi-Z
12
12
20
20
20
-
A8 A7 A6 A5 A4 A3 A2 A1 A0
A8 A7 A6 A5 A4 A3 A2 A1 A0
-
D7 - D0
D7 - D0
D7 - D0
(RDY/~BSY)
(RDY/~BSY)
0
1 X X X X X X X
Table 10.6 Microwire Command Set for 11 Address Bits
DATA TO
START
BIT
DATA FROM
EEPROM
# OF
CLOCKS
INST
OPCODE
ADDRESS
EEPROM
A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
ERASE
ERAL
1
1
1
1
1
1
1
11
00
00
00
10
01
00
-
(RDY/~BSY)
(RDY/~BSY)
Hi-Z
14
14
14
14
22
22
22
1
0
1
0
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
-
EWDS
EWEN
READ
WRITE
WRAL
-
-
Hi-Z
A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
-
D7 - D0
D7 - D0
D7 - D0
(RDY/~BSY)
(RDY/~BSY)
0
1 X X X X X X X X X
10.2.3.2
ERASE (Erase Location)
If erase/write operations are enabled in the EEPROM, this command will erase the location selected
by the EPC_ADDRESS field of the EEPROM Command Register (E2P_CMD). The EPC_TIMEOUT
bit is set if the EEPROM does not respond within 30mS.
EECS
EECLK
EEDO
EEDI
1
1
1
Ax
A0
Figure 10.7 EEPROM ERASE Cycle
SMSC LAN9312
145
Revision 1.2 (04-08-08)
DATASHEET
SMSC [ SMSC CORPORATION ]
