High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
Datasheet
Figure 10.2 displays the various bus states of a typical I2C cycle.
data
can
change
data
can
change
data
can
change
data
can
change
data
stable
data
stable
EE_SDA
EE_SCL
S
Sr
P
Data Valid
or Ack
Data Valid
or Ack
Re-Start
Condition
Stop Condition
Start Condition
Figure 10.2 I2C Cycle
2
10.2.2.2
I C EEPROM Device Addressing
The I2C EEPROM is addressed for a read or write operation by first sending a control byte followed
by the address byte or bytes. The control byte is preceded by a start condition. The control byte and
address byte(s) are each acknowledged by the EEPROM slave. If the EEPROM slave fails to send an
acknowledge, then the sequence is aborted and the EPC_TIMEOUT bit of the EEPROM Command
Register (E2P_CMD) is set.
The control byte consists of a 4-bit control code, 3-bits of chip/block select and one direction bit. The
control code is 1010b. For single byte addressing EEPROMs, the chip/block select bits are used for
address bits 10, 9, and 8. For double byte addressing EEPROMs, the chip/block select bits are set
low. The direction bit is set low to indicate the address is being written.
Figure 10.3 illustrates typical I2C EEPROM addressing bit order for single and double byte addressing.
Address High
Byte
Address Low
Byte
Control Byte
Address Byte
Control Byte
A
1
0
A
C
K
A
C
K
A
C
K
A
1
5
A
1
4
A
1
3
A
1
2
A
1
1
A
1
0
A
C
K
A
C
K
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
S
1
0
1
0
0
S 1 0 1 0 0 0 0 0
Chip / Block R/~W
Select Bits
Chip / Block R/~W
Select Bits
Single Byte Addressing
Double Byte Addressing
Figure 10.3 I2C EEPROM Addressing
SMSC LAN9312
141
Revision 1.2 (04-08-08)
DATASHEET
SMSC [ SMSC CORPORATION ]
