High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
Datasheet
2
10.2.2.3
I C EEPROM Byte Read
Following the device addressing, a data byte may be read from the EEPROM by outputting a start
condition and control byte with a control code of 1010b, chip/block select bits as described in
Section 10.2.2.2, and the R/~W bit high. The EEPROM will respond with an acknowledge, followed by
8-bits of data. If the EEPROM slave fails to send an acknowledge, then the sequence is aborted and
the EPC_TIMEOUT bit in the EEPROM Command Register (E2P_CMD) is set. The I2C master then
sends a no-acknowledge, followed by a stop condition.
Figure 10.4 illustrates typical I2C EEPROM byte read for single and double byte addressing.
Control Byte
Data Byte
Control Byte
Data Byte
A
C
K
A
1
0
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
A
9
A
8
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
S
1
0
1
0
1
P
S
1
0
1
0
0
0
0
1
P
Chip / Block R/~W
Select Bits
Chip / Block R/~W
Select Bits
Single Byte Addressing Read
Double Byte Addressing Read
Figure 10.4 I2C EEPROM Byte Read
For a register level description of a read operation, refer to Section 10.2.1, "EEPROM Controller
Operation," on page 138.
2
10.2.2.4
I C EEPROM Sequential Byte Reads
Following the device addressing, data bytes may be read sequentially from the EEPROM by outputting
a start condition and control byte with a control code of 1010b, chip/block select bits as described in
Section 10.2.2.2, and the R/~W bit high. The EEPROM will respond with an acknowledge, followed by
8-bits of data. If the EEPROM slave fails to send an acknowledge, then the sequence is aborted and
the EPC_TIMEOUT bit in the EEPROM Command Register (E2P_CMD) is set. The I2C master then
sends an acknowledge, and the EEPROM responds with the next 8-bits of data. This continues until
the last desired byte is read, at which point the I2C master sends a no-acknowledge, followed by a
stop condition.
Figure 10.4 illustrates typical I2C EEPROM sequential byte reads for single and double byte
addressing.
Control Byte
Data Byte
Data Byte
Data Byte
A
C
K
A
1
0
A
C
K
A
C
K
A
A
C
K
A
9
A
8
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
C ...
S
1
0
1
0
1
P
K
R/~W
Chip / Block
Select Bits
Single Byte Addressing Sequential Reads
Control Byte
Data Byte
Data Byte
Data Byte
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
S
1
0
1
0
0
0
0
1
...
P
Chip / Block R/~W
Select Bits
Double Byte Addressing Sequential Reads
Figure 10.5 I2C EEPROM Sequential Byte Reads
Revision 1.2 (04-08-08)
142
SMSC LAN9312
DATASHEET
SMSC [ SMSC CORPORATION ]
