欢迎访问ic37.com |
会员登录 免费注册
发布采购

LAN9210 参数 Datasheet PDF下载

LAN9210图片预览
型号: LAN9210
PDF下载: 下载PDF文件 查看货源
内容描述: 外形小巧单芯片以太网控制器与HP Auto-MDIX的 [Small Form Factor Single- Chip Ethernet Controller with HP Auto-MDIX]
分类和应用: 控制器以太网
文件页数/大小: 458 页 / 4618 K
品牌: SMSC [ SMSC CORPORATION ]
 浏览型号LAN9210的Datasheet PDF文件第139页浏览型号LAN9210的Datasheet PDF文件第140页浏览型号LAN9210的Datasheet PDF文件第141页浏览型号LAN9210的Datasheet PDF文件第142页浏览型号LAN9210的Datasheet PDF文件第144页浏览型号LAN9210的Datasheet PDF文件第145页浏览型号LAN9210的Datasheet PDF文件第146页浏览型号LAN9210的Datasheet PDF文件第147页  
High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface  
Datasheet  
Sequential reads are used by the EEPROM Loader. Refer to Section 10.2.4, "EEPROM Loader" for  
additional information.  
For a register level description of a read operation, refer to Section 10.2.1, "EEPROM Controller  
Operation," on page 138.  
2
10.2.2.5  
I C EEPROM Byte Writes  
Following the device addressing, a data byte may be written to the EEPROM by outputting the data  
after receiving the acknowledge from the EEPROM. The data byte is acknowledged by the EEPROM  
2
slave and the I C master finishes the write cycle with a stop condition. If the EEPROM slave fails to  
send an acknowledge, then the sequence is aborted and the EPC_TIMEOUT bit in the EEPROM  
Command Register (E2P_CMD) is set.  
2
Following the data byte write cycle, the I C master will poll the EEPROM to determine when the byte  
write is finished. A start condition is sent followed by a control byte with a control code of 1010b,  
chip/block select bits low, and the R/~W bit low. If the EEPROM is finished with the byte write, it will  
2
respond with an acknowledge. Otherwise, it will respond with a no-acknowledge and the I C master  
2
will repeat the poll. If the acknowledge does not occur within 30mS, a time-out occurs. Once the I C  
master receives the acknowledge, it concludes by sending a start condition, followed by a stop  
condition, which will place the EEPROM into standby.  
2
Figure 10.4 illustrates typical I C EEPROM byte write.  
Conclude  
Data Cycle  
Data Byte  
Poll Cycle  
Poll Cycle  
Poll Cycle  
Control Byte  
Control Byte  
Control Byte  
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
... S  
P
S
1
0
1
0
0
0
0
0
S
1
0
1
0
0
0
0
0
1
0
1
0
0
0
0
0
S P  
R/~W  
R/~W  
R/~W  
Chip / Block  
Select Bits  
Chip / Block  
Select Bits  
Chip / Block  
Select Bits  
Figure 10.6 I2C EEPROM Byte Write  
For a register level description of a write operation, refer to Section 10.2.1, "EEPROM Controller  
Operation," on page 138.  
SMSC LAN9312  
143  
Revision 1.2 (04-08-08)  
DATASHEET  
 复制成功!