High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
Datasheet
10.2.3.7
WRITE (Write Location)
If erase/write operations are enabled in the EEPROM, this command will cause the contents of the
EEPROM Data Register (E2P_DATA) to be written to the EEPROM location pointed to by the
EPC_ADDRESS field of the EEPROM Command Register (E2P_CMD). The EPC_TIMEOUT bit of the
EEPROM Command Register (E2P_CMD) is set if the EEPROM does not respond within 30mS.
EECS
EECLK
EEDO
EEDI
1
0
1
Ax
A0
D7
D0
Figure 10.12 EEPROM WRITE Cycle
10.2.3.8
WRAL (Write All)
If erase/write operations are enabled in the EEPROM, this command will cause the contents of the
EEPROM Data Register (E2P_DATA) to be written to every EEPROM memory location. The
EPC_TIMEOUT bit of the EEPROM Command Register (E2P_CMD) is set if the EEPROM does not
respond within 30mS.
EECS
EECLK
EEDO
EEDI
1
0
0
0
1
D7
D0
Figure 10.13 EEPROM WRAL Cycle
Revision 1.2 (04-08-08)
148
SMSC LAN9312
DATASHEET
SMSC [ SMSC CORPORATION ]
