FEAST Fast Ethernet Controller for PCMCIA and Generic 16-Bit Applications
1. Allocate Command
2. Poll ALLOC_INT bit until set
3. Read Allocation Result Register
ALLOCATED PACKET NUMBER - Packet number associated with the last memory allocation request. The value is only
valid if the FAILED bit is clear.
Note: For software compatibility with future versions, the value read from the ARR after an allocation request is intended
to be written into the PNR as is, without masking higher bits (provided FAILED = 0).
BANK 2
OFFSET
4
NAME
FIFO PORTS REGISTER
TYPE
READ ONLY
SYMBOL
FIFO
This register provides access to the read ports of the Receive FIFO and the Transmit completion FIFO. The packet
numbers to be processed by the interrupt service routines are read from this register.
HIGH
BYTE
REMPTY
0
RX FIFO PACKET NUMBER
1
0
0
0
0
0
0
0
0
0
0
0
0
LOW
TEMPTY
TX FIFO PACKET NUMBER
BYTE
1
0
0
0
REMPTY - No receive packets queued in the RX FIFO. For polling purposes, uses the RCV_INT bit in the Interrupt Status
Register.
TOP OF RX FIFO PACKET NUMBER - Packet number presently at the output of the RX FIFO. Only valid if REMPTY is
clear. The packet is removed from the RX FIFO using MMU Commands 3) or 4).
TEMPTY - No transmit packets in completion queue. For polling purposes, uses the TX_INT bit in the Interrupt Status
Register.
TX FIFO PACKET NUMBER - Packet number presently at the output of the TX FIFO. Only valid if TEMPTY is clear. The
packet is removed when a TX INT acknowledge is issued.
Note: For software compatibility with future versions, the value read from each FIFO register is intended to be written into
the PNR as is, without masking higher bits (provided TEMPTY and REMPTY = 0 respectively).
SMSC DS – LAN91C110 REV. B
Page 27
Rev. 09/05/02
SMSC [ SMSC CORPORATION ]
