FEAST Fast Ethernet Controller for PCMCIA and Generic 16-Bit Applications
BANK 1
OFFSET
NAME
CONTROL REGISTER
TYPE
READ/WRITE
SYMBOL
CTR
C
HIGH BYTE
RCV_
BAD
AUTO
Reserved
0
Reserved
0
1
Reserved
1
1
Reserved
RELEASE
0
1
1
0
0
0
LOW BYTE
LE
CR
TE
Reserved
Reserved
Reserved
Reserved
ENABLE
ENABLE
ENABLE
0
0
0
1
0
0
0
0
RCV_BAD - When set, bad CRC packets are received. When clear bad CRC packets do not generate interrupts and their
memory is released.
AUTO RELEASE - When set, transmit pages are released by transmit completion if the transmission was successful
(when TX_SUC is set). In that case there is no status word associated with its packet number, and successful packet
numbers are not even written into the TX COMPLETION FIFO. A sequence of transmit packets will generate an interrupt
only when the sequence is completely transmitted (TX EMPTY INT will be set), or when a packet in the sequence
experiences a fatal error (TX INT will be set). Upon a fatal error TXENA is cleared and the transmission sequence stops.
The packet number that failed, is present in the FIFO PORTS register, and its pages are not released, allowing the CPU
to restart the sequence after corrective action is taken.
LE ENABLE - Link Error Enable. When set it enables the LINK_OK bit transition as one of the interrupts merged into the
EPH INT bit. Clearing the LE ENABLE bit after an EPH INT interrupt, caused by a LINK_OK transition, will acknowledge
the interrupt. LE ENABLE defaults low (disabled).
CR ENABLE - Counter Roll over Enable. When set, it enables the CTR_ROL bit as one of the interrupts merged into the
EPH INT bit. Reading the COUNTER register after an EPH INT interrupt caused by a counter rollover, will acknowledge
the interrupt. CR ENABLE defaults low (disabled).
TE ENABLE - Transmit Error Enable. When set it enables Transmit Error as one of the interrupts merged into the EPH
INT bit. An EPH INT interrupt caused by a transmitter error is acknowledged by setting TXENA bit in the TCR register to 1
or by clearing the TE ENABLE bit. TE ENABLE defaults low (disabled). Transmit Error is any condition that clears TXENA
with TX_SUC staying low as described in the EPHSR register.
Reserved 2-0: These reserved bits must always be written to as zero(0).
SMSC DS – LAN91C110 REV. B
Page 24
Rev. 09/05/02
SMSC [ SMSC CORPORATION ]
