FEAST Fast Ethernet Controller for PCMCIA and Generic 16-Bit Applications
DATA REGISTER - Used to read or write the data buffer byte/word presently addressed by the pointer register.
This register is mapped into two uni-directional FIFOs that allow moving words to and from the LAN91C110 regardless of
whether the pointer address is even, odd or dword aligned. Data goes through the write FIFO into memory, and is pre-
fetched from memory into the read FIFO. If byte accesses are used, the appropriate (next) byte can be accessed through
the Data Low or Data High registers. The order to and from the FIFO is preserved. Byte word accesses can be mixed on
the fly in any order.
This register is mapped into two consecutive word locations. The DATA register is accessible at any address in the 8
through Ah range, while the number of bytes being transferred is determined by A1 and nBE0-nBE. The FIFOs are 12
bytes each.
BANK 2
OFFSET
C
NAME
TYPE
READ ONLY
SYMBOL
IST
INTERRUPT STATUS REGISTER
RX_OVRN
INT
TX
EMPTY
INT
ERCV INT
0
EPH INT
0
ALLOC
INT
TX INT
0
RCV INT
0
0
0
1
0
OFFSET
C
NAME
TYPE
WRITE ONLY
SYMBOL
ACK
INTERRUPT ACKNOWLEDGE
REGISTER
RX_OVRN
INT
TX
EMPTY
INT
ERCV INT
TX INT
OFFSET
D
NAME
INTERRUPT MASK REGISTER
TYPE
READ/WRITE
SYMBOL
MSK
RX_OVRN
INT
TX
EMPTY
INT
ERCV
INT
EPH INT
MASK
ALLOC
INT
TX INT
MASK
RCV INT
MASK
MASK
MASK
0
MASK
0
MASK
0
0
0
0
0
0
This register can be read and written as a word or as two individual bytes.
The Interrupt Mask Register bits enable the appropriate bits when high and disable them when low. A MASK bit being set
will cause a hardware interrupt.
Note: The Bit 7 mask must never be written high (1).
SMSC DS – LAN91C110 REV. B
Page 29
Rev. 09/05/02
SMSC [ SMSC CORPORATION ]
