FEAST Fast Ethernet Controller for PCMCIA and Generic 16-Bit Applications
The I/O base decode defaults to 300h (namely, the high byte defaults to 18h).
Reserved - Must be 0.
BANK 1
OFFSET
NAME
TYPE
READ/WRITE
SYMBOL
IAR
4 THROUGH 9 INDIVIDUAL ADDRESS REGISTERS
These registers are required to be written by the host following power-up and hardware reset. For PC Card
designs, the CIS contains the node address. The S/W driver must load that address into these registers. The
registers are modified by the software driver. Bit 0 of Individual Address 0 register corresponds to the first bit of
the address on the cable.
LOW
ADDRESS 0
BYTE
0
0
0
0
0
0
0
0
HIGH
BYTE
ADDRESS 1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
LOW
ADDRESS 2
BYTE
0
0
HIGH
BYTE
ADDRESS 3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
LOW
ADDRESS 4
BYTE
0
0
HIGH
BYTE
ADDRESS 5
0
0
0
0
0
0
0
0
BANK 1
OFFSET
A
NAME
TYPE
SYMBOL
Reserved.
SMSC DS – LAN91C110 REV. B
Page 23
Rev. 09/05/02
SMSC [ SMSC CORPORATION ]
