FEAST Fast Ethernet Controller for PCMCIA and Generic 16-Bit Applications
ERCV INT - Early receive interrupt. Set whenever a receive packet is being received, and the number of bytes received
into memory exceeds the value programmed as ERCV THRESHOLD (Bank 3, Offset Ch). ERCV INT stays set until
acknowledged by writing the INTERRUPT ACKNOWLEDGE REGISTER with the ERCV INT bit set.
EPH INT - Set when the Ethernet Protocol Handler section indicates one out of various possible special conditions. This
bit merges exception type of interrupt sources, whose service time is not critical to the execution speed of the low level
drivers. The exact nature of the interrupt can be obtained from the EPH Status Register (EPHSR), and enabling of these
sources can be done via the Control Register. The possible sources are:
1. LINK - Link Test transition
2. CTR_ROL - Statistics counter roll over
3. TXENA cleared - A fatal transmit error occurred forcing TXENA to be cleared. TX_SUC will be low and the specific
reason will be reflected by the bits:
3.1) TXUNRN - Transmit under-run
3.2) SQET - SQE Error
3.3) LOST CARR - Lost Carrier
3.4) LATCOL - Late Collision
3.5) 16COL - 16 collisions
Any of the above interrupt sources can be masked by the appropriate ENABLE bits in the Control Register. 1) LE
ENABLE (Link Error Enable), 2) CR ENABLE (Counter Roll Over), 3) TE ENABLE (Transmit Error Enable)
EPH INT will only be cleared by the following methods:
1. Clearing the LE ENABLE bit in the Control Register if an EPH interrupt is caused by a LINK_OK transition.
2. Reading the Counter Register if an EPH interrupt is caused by statistics counter roll over.
3. Setting TXENA bit high if an EPH interrupt is caused by any of the fatal transmit error listed above (3.1 to 3.5).
RX_OVRN INT - Set when 1) the receiver aborts due to an overrun due to a failed memory allocation, 2) the receiver
aborts due to a packet length of greater than 2K bytes, or 3) the receiver aborts due to the RCV DISCRD bit in the ERCV
register set. The RX_OVRN INT bit latches the condition for the purpose of being polled or generating an interrupt, and
will only be cleared by writing the acknowledge register with the RX_OVRN INT bit set.
ALLOC INT - Set when an MMU request for TX ram pages is successful. This bit is the complement of the FAILED bit
in the ALLOCATION RESULT register. The ALLOC INT bit is cleared by the MMU when the next allocation request
is processed or allocation fails.
TX EMPTY INT - Set if the TX FIFO goes empty, can be used to generate a single interrupt at the end of a sequence of
packets enqueued for transmission. This bit latches the empty condition, and the bit will stay set until it is specifically
cleared by writing the acknowledge register with the TX EMPTY INT bit set. If a real time reading of the FIFO empty is
desired, the bit should be first cleared and then read.
The TX_EMPTY MASK bit should only be set after the following steps:
1. A packet is enqueued for transmission
2. The previous empty condition is cleared (acknowledged)
TX INT - Set when at least one packet transmission was completed or any of the below transmit fatal errors occurs:
1. TXUNRN - Transmit under-run
2. SQET - SQE Error
3. LOST CARR - Lost Carrier
4. LATCOL - Late Collision
5. 16COL - 16 collisions
The first packet number to be serviced can be read from the FIFO PORTS register. The TX INT bit is always the logic
complement of the TEMPTY bit in the FIFO PORTS register. After servicing a packet number, its TX INT interrupt is
removed by writing the Interrupt Acknowledge Register with the TX INT bit set.
RCV INT - Set when a receive interrupt is generated. The first packet number to be serviced can be read from the FIFO
PORTS register. The RCV INT bit is always the logic complement of the REMPTY bit in the FIFO PORTS register.
Receive Interrupt is cleared when RX FIFO is empty.
SMSC DS – LAN91C110 REV. B
Page 30
Rev. 09/05/02
SMSC [ SMSC CORPORATION ]
