BANK1
OFFSET
0
NAME
TYPE
READ/WRITE
SYMBOL
CR
CONFIGURATION REGISTER
The Configuration Register holds bits that define the adapter configuration and are not expected to change during run-
time. This register is part of the EEPROM saved setup.
HIGH
BYTE
MII
FULL
STEP
AUI
Reserved
NO WAIT
Reserved
0
Reserved
SELECT
SELECT
1
1
0
1
1
0
0
0
0
LOW
Reserved
Reserved
INT SEL1
INT SEL0
BYTE
1
0
1
0
0
0
1
MII SELECT - Used to select the network interface port. When set, the LAN91C110 will use its MII port and interface a
PHY device at the nibble rate. This bit must always be set for proper chip function.
NO WAIT - When set, does not request additional wait states. An exception to this are accesses to the Data Register if not
ready for a transfer. When clear, negates ARDY for two to three clocks on any cycle to the LAN91C110.
FULL STEP - Reserved
AUI SELECT - This bit is a general purpose output port. Its value drives pin AUISEL and can be used as a general
purpose non-volatile configuration pin. Defaults low.
Reserved - Must be 0.
INT SEL1-0 - Used to select interrupt pin. The bits must remain 00 for the interrupt pin to be asserted for interrupt
indication. All other bit combinations are undefined.
BANK 1
OFFSET
2
NAME
TYPE
READ/WRITE
SYMBOL
BAR
BASE ADDRESS REGISTER
This register holds the I/O address decode option chosen for the LAN91C110. Is not usually modified during run-time.
HIGH
BYTE
A15
0
A14
0
A13
0
A9
A8
1
A7
0
A6
0
A5
1
0
1
LOW
Reserved
BYTE
0
0
0
0
0
0
0
1
A15 - A13 and A9 - A5 - These bits are compared against the I/O address on the bus to determine the IOBASE for the
LAN91C110‘s registers. The 64k I/O space is fully decoded by the LAN91C110 down to a 16 location space, therefore the
unspecified address lines A4, A10, A11 and A12 must be all zeros.
SMSC DS – LAN91C110 REV. B
Page 22
Rev. 09/05/02
SMSC [ SMSC CORPORATION ]
