FEAST Fast Ethernet Controller for PCMCIA and Generic 16-Bit Applications
All memory related information is represented in 256 * M byte units, where the multiplier M is determined by the MCR
upper byte.
These register default to FFh, which should be interpreted as 256.
BANK 0
OFFSET
A
NAME
MEMORY CONFIGURATION
REGISTER
TYPE
SYMBOL
MCR
Lower Byte -
READ/WRITE
Upper Byte -
READ ONLY
HIGH
BYTE
MEMORY SIZE MULTIPLIER
0
0
0
1
1
0
1
0
1
0
LOW
MEMORY RESERVED FOR TRANSMIT (IN BYTES * 256 * M)
BYTE
0
0
0
0
0
0
MEMORY RESERVED FOR TRANSMIT - Programming this value allows the host CPU to reserve memory to be used
later for transmit, limiting the amount of memory that receive packets can use. When programmed for zero, the memory
allocation between transmit and receive is completely dynamic. When programmed for a non-zero value, the allocation is
dynamic if the free memory exceeds the programmed value, while receive allocation requests are denied if the free
memory is less or equal to the programmed value. This register defaults to zero upon reset. It is not affected by the
RESET MMU command.
The value written to the MCR is a reserved memory space IN ADDITION TO ANY MEMORY CURRENTLY IN USE. If the
memory allocated for transmit plus the reserved space for transmit is required to be constant (rather than grow with
transmit allocations) the CPU should update the value of this register after allocating or releasing memory.
The contents of the MIR as well as the low byte of the MCR are specified in units of 256 * M bytes, where M is the
Memory Size Multiplier. M=2 for the LAN91C110. A value of 04h in the lower byte of the MCR is equal to one 2K page (4
* 256 *2 = 2K); since memory must be reserved in multiples of pages, bits 0 and 1 of the MCR should be written to 1 only
when the entire memory is being reserved for transmit (i.e., low byte of MCR = FFh).
SMSC DS – LAN91C110 REV. B
Page 21
Rev. 09/05/02
SMSC [ SMSC CORPORATION ]
