Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet
NEXT STATE
ECOR
FUNC
ECSR
CTR
PWRDWN
BIT
CTR
WAKEUP_EN
BIT
PWR DWN PIN
(A= ASSRTD)
NO.
WAKES UP BY
PWR
COMMENTS
ENABLE
DOWN
4
By writing a 0 to
CTR PWRDWN and
0 to WAKEUP_EN
bits
nA
1
0
0
0
5
6
By writing 1 to
nA
1
0
0
0
Note: Both
Power down
bits need to be
written as 0
only if both
ECOR Func Enable,
0 to ECSR Power
Down, 0 to CTR
PWRDWN
were set to 1
By writing 1 to
nA
1
0
0
0
Note: Both
Power down
bits need to be
written as 0
only if both
ECOR Func Enable,
0 to ECSR Power
Down, 0 to CTR
PWRDWN, and 0 to
WAKEUP_EN bit
were set to 1
7
By writing 0 to
ECSR Power Down
bit*
nA
nA
1
1
0
0
0
0
0
0
7S
By writing 0 to
Note: Both
Power down
bits need to be
written as 0
only if both
ECSR Power Down
and a 0 to CTR
PWRDWN bit
were set to 1
8
By writing 0 to
nA
nA
1
1
0
0
0
0
0
0
ECSR Power Down
and writing CTR
PWRDWN bit = 0 &
WAKEUP_EN = 0, if
needed
8S
By writing 0 to
ECSR Power Down
and writing CTR
PWRDWN bit = 0 &
WAKEUP_EN = 0, if
needed
PCMCIA Attribute Memory
Address 0- 7FFEh
The Attribute Memory is implemented using an external parallel EEPROM, ROM or Flash ROM. A parallel
EEPROM (or equivalent external device) must be used for CIS.
In LOCAL BUS mode, serial EEPROM is used for configuration and IEEE Node address making it software
compatible to the LAN9xxx family of Ethernet LAN Controllers. The EEPROM is optional for both LOCAL BUS
and PCMCIA requiring a Minimum size of 64 X 16 bit word addresses.
The LAN91C96 generates the appropriate control lines (nFCS and nFWE) to read and write the Attribute
memory, and it tri-states the data bus during external Attribute Memory accesses. Only even locations are
used.
Rev. 09/10/2004
Page 34
SMSC LAN91C965v&3v
DATASHEET
SMSC [ SMSC CORPORATION ]
