Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet
register are not accessible) is allowed. IREQ is not generated for this function and INPACK* is not
returned for accesses to the Ethernet registers.
Note:
Magic packet bit setting is ignored if the function is disabled.
8002h - Ethernet Configuration and Status Register (ECSR)
7
6
5
IOIs8
0
4
3
2
Pwrdwn
0
1
Intr
0
0
0
0
0
0
0
BIT 7 - Not defined
BIT 6 - Not defined
BIT 5 - IOIs8: This bit when set, indicates that the Host can only do 8 bit cycles (on D7-0). The Ethernet
function is forced in this case to eight bit mode regardless of the EN16* pin and 16BIT value. This bit also
disables (floats) the IOIs16 signal.
BIT 4 - Not defined
BIT 3 - Not defined
BIT 2 - PwrDwn: When set (1), this bit puts the LAN91C96 Ethernet function into power down mode. The
Ethernet function is also put into power down mode when the Enable Function bit (ECOR bit 0 in PCMCIA
only) is cleared. Refer to the Power Down Logic section for additional information.
BIT 1 - Intr: This bit is read/set to a one when this function is requesting interrupt service. When this bit is
set, IREQOut is asserted.
BIT 0 - Not Defined
Rev. 09/10/2004
Page 36
SMSC LAN91C965v&3v
DATASHEET
SMSC [ SMSC CORPORATION ]
