10/100 Non-PCI Ethernet Single Chip MAC + PHY
Datasheet
DPLX - Duplex mode
When Auto Negotiation is disabled this bit can be used to manually select the link duplex state. Writing
a ‘1’ to this bit selects full duplex while a ‘0’ selects half duplex.
When Auto-Negotiation is enabled reading or writing this bit has no effect.
COLTST - Collision test
Setting a ‘1’ allows for testing of the MII COL signal. ‘0’ allows normal operation.
Reserved:Reserved, Must be 0 for Proper Operation
9.2
Register 1. Status Register
CAP_T4
CAP_TXF
CAP_TXH
CAP_TF
CAP_TH
Reserved
Reserved.
Reserved
R
0
R
1
R
1
R
1
R
1
R
0
R
0
R
0
Reserved
CAP_SUPR
ANEG_ACK
REM_FLT
R, LH
0
CAP_ANEG
LINK
R, LL
0
JAB
R, LH
0
EXREG
R
0
R
0
R
0
R
1
R
1
CAP_T4 - 100BASE-T4 Capable
‘1’ Indicates 100Base-T4 capable PHY, ‘0’ not capable.
CAP_TXF - 100BASE-TX Full Duplex Capable
‘1’ Indicates 100Base-X full duplex capable PHY, ‘0’ not capable.
CAP_TXH - 100BASE-TX Half Duplex Capable
‘1’ Indicates 100Base-X alf duplex capable PHY, ‘0’ not capable.
CAP_TF - 10BASE-T Full Duplex Capable
‘1’ Indicates 10Mbps full duplex capable PHY, ‘0’ not capable.
CAP_TH - 10BASE-T Half Duplex Capable
‘1’ Indicates 10Mbps half duplex capable PHY, ‘0’ not capable.
Reserved:Reserved, Must be 0 for Proper Operation.
CAP_SUPR - MI Preamble Suppression Capable
‘1’ indicates the PHY is able to receive management frames even if not preceded by a preamble. ‘0’
when it is not able.
ANEG_ACK - Auto-Negotiation Acknowledgment
When read as ‘1’ indicate ANEG has been completed and that contents in registers 4,5,6 and 7 are
valid. ‘0’ means ANEG has not completed and contents in registers 4,5,6 and 7 are meaningless. The
PHY returns zero if ANEG is disabled.
Revision 1.8 (07-13-05)
SMSC LAN91C111-REV B
DATA8S6HEET
SMSC [ SMSC CORPORATION ]
