10/100 Non-PCI Ethernet Single Chip MAC + PHY
Datasheet
9.1
Register 0. Control Register
RST
LPBK
RW
0
SPEED
RW
ANEG_EN
PDN
RW
0
MII_DIS
ANEG_RST
RW. SC
0
DPLX
RW
0
RW, SC
0
RW
1
RW
1
1
COLST
RW
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
0
RST - Reset
A ‘1’ written to this bit will initiate a reset of the PHY. The bit is self-clearing, and the PHY will return
a ‘1’ on reads to this bit until the reset is completed. Write transactions to this register may be ignored
while the PHY is processing the reset. All PHY registers will be driven to their default states after a
reset. The internal PHY is guaranteed to be ready for normal operation 50 mS after the RST bit is
set. Software driver requires to wait for 50mS after setting the RST bit to high to access the internal
PHY again.
LPBK - Loopback
Writing a ‘1’ will put the PHY into loopback mode.
Speed (Speed Selection)
When Auto Negotiation is disabled this bit can be used to manually select the link speed. Writing a
‘1’ to this bit selects 100 Mbps, a ‘0’ selects 10 Mbps.
When Auto-Negotiation is enabled reading or writing this bit has no meaning/effect.
ANEN_EN - Auto-Negotiation Enable
Auto-negotiation (ANEG) is on when this bit is ‘1’. In that case the contents of bits Speed and Duplex
are ignored and the ANEG process determines the link configuration.
PDN - Power down
Setting this bit to ‘1’ will put the PHY in PowerDown mode. In this state the PHY will respond to
management transactions.
MII_DIS - MII DISABLE
Setting this bit will set the PHY to an isolated mode in which it will respond to MII management frames
over the MII management interface but will ignore data on the MII data interface. The internal PHY
is placed in isolation mode at power up and reset. It can be removed from isolation mode by clearing
the MII_DIS bit in the PHY Control Register. If necessary, the internal PHY can be enabled by clearing
the EXT_PHY bit in the Configuration Register.
ANEG_RST - Auto-Negotiation Reset
This bit will return 0 if the PHY does not support ANEG or if ANEG is disabled through the ANEG_EN
bit. If neither of the previous is true, setting this bit to ‘1’ resets the ANEG process. This bit is self
clearing and the PHY will return a ‘1’ until ANEG is initiated, writing a ‘0’ does not affect the ANEG
process.
SMSC LAN91C111-REV B
Revision 1.8 (07-13-05)
DATA8S5HEET
SMSC [ SMSC CORPORATION ]
