10/100 Non-PCI Ethernet Single Chip MAC + PHY
Datasheet
REGISTER ADDRESS
REGISTER NAME
17
18
19
20
Configuration 2
Status Output
Mask
Reserved
PHY Register Description
Table 9.1 MII Serial Frame Structure
<Idle>
IDLE
<Start>
ST[1:0]
<Read>
READ
<Write>
WRITE
<PHY Addr.>
PHYAD[4:0]
<REG.Addr.>
REGAD[4:0]
<Turnaround>
TA[1:0]
<Data>
D[15:0]
D[15:0]
↓
Register 0
Register 1
Register 2
Register 3
Register 4
Register 5
Register 16
Register 17
Register 18
Register 19
Register 20
Control
Status
PHY ID#1
PHY ID#2
AutoNegotiation Advertisement
AutoNegotiation Remote End Capability
Configuration 1
Configuration 2
Status Output
Mask
Reserved
SYMBOL
NAME
DEFINITION
R/W
IDLE
Idle Pattern
These bits are an idle pattern. Device will not initiate an MI cycle until
it detects at least 32 1's
W
ST1
ST0
Start Bits
When ST[1:0]=01, a MI Serial Port access cycle starts.
W
READ
Read Select
Write Select
1 = Read Cycle
1 = Write Cycle
W
W
WRITE
PHYAD[4:0]
Physical
Device
PHYSICAL ADDRESS
R
Address
Revision 1.8 (07-13-05)
SMSC LAN91C111-REV B
DATA8S2HEET
SMSC [ SMSC CORPORATION ]
