10/100 Non-PCI Ethernet Single Chip MAC + PHY
Datasheet
8.15
Bank 1 - Control Register
OFFSET
C
NAME
TYPE
SYMBOL
CTR
CONTROL REGISTER
READ/WRITE
HIGH
Reserved
RCV_
Reserved
0
Reserved
AUTO
Reserved
Reserved Reserved
BYTE
BAD
0
RELEASE
0
1
0
0
1
0
LOW BYTE
LE
CR
TE
Reserved
Reserved EEPROM
SELECT
RELOAD
STORE
ENABLE
ENABLE
ENABLE
0
0
0
1
0
0
0
0
RCV_BAD - When set, bad CRC packets are received. When clear bad CRC packets do not generate
interrupts and their memory is released.
AUTO RELEASE - When set, transmit pages are released by transmit completion if the transmission
was successful (when TX_SUC is set). In that case there is no status word associated with its packet
number, and successful packet numbers are not even written into the TX COMPLETION FIFO.
A
sequence of transmit packets will generate an interrupt only when the sequence is completely
transmitted (TX EMPTY INT will be set), or when a packet in the sequence experiences a fatal error
(TX INT will be set). Upon a fatal error TXENA is cleared and the transmission sequence stops. The
packet number that failed, is present in the FIFO PORTS register, and its pages are not released,
allowing the CPU to restart the sequence after corrective action is taken.
LE ENABLE - Link Error Enable. When set it enables the LINK_OK bit transition as one of the
interrupts merged into the EPH INT bit. Clearing the LE ENABLE bit after an EPH INT interrupt, caused
by a LINK_OK transition, will acknowledge the interrupt. LE ENABLE defaults low (disabled).
CR ENABLE - Counter Roll over Enable. When set, it enables the CTR_ROL bit as one of the
interrupts merged into the EPH INT bit. Reading the COUNTER register after an EPH INT interrupt
caused by a counter rollover, will acknowledge the interrupt. CR ENABLE defaults low (disabled).
TE ENABLE - Transmit Error Enable. When set it enables Transmit Error as one of the interrupts
merged into the EPH INT bit. An EPH INT interrupt caused by a transmitter error is acknowledged by
setting TXENA bit in the TCR register to 1 or by clearing the TE ENABLE bit. TE ENABLE defaults
low (disabled). Transmit Error is any condition that clears TXENA with TX_SUC staying low as
described in the EPHSR register.
EEPROM SELECT - This bit allows the CPU to specify which registers the EEPROM RELOAD or
STORE refers to. When high, the General Purpose Register is the only register read or written. When
low, RELOAD reads Configuration, Base and Individual Address, and STORE writes the Configuration
and Base registers.
RELOAD - When set it will read the EEPROM and update relevant registers with its contents. Clears
upon completing the operation.
STORE - When set, stores the contents of all relevant registers in the serial EEPROM. Clears upon
completing the operation.
Note: When an EEPROM access is in progress the STORE and RELOAD bits will be read back as
high. The remaining 14 bits of this register will be invalid. During this time attempted read/write
operations, other than polling the EEPROM status, will NOT have any effect on the internal
registers. The CPU can resume accesses to the LAN91C111 after both bits are low. A worst
case RELOAD operation initiated by RESET or by software takes less than 750 µs.
SMSC LAN91C111-REV B
Revision 1.8 (07-13-05)
DATA6S7HEET
SMSC [ SMSC CORPORATION ]
