10/100 Non-PCI Ethernet Single Chip MAC + PHY
Datasheet
OPERATION
CODE
DECIMAL
VALUE
COMMAND
111
7
RESET TX FIFOs - This command will reset both TX FIFOs: The TX FIFO
holding the packet numbers awaiting transmission and the TX Completion FIFO.
This command provides a mechanism for canceling packet transmissions, and
reordering or bypassing the transmit queue. The RESET TX FIFOs command
should only be used when the transmitter is disabled. Unlike the RESET MMU
command, the RESET TX FIFOs does not release any memory.
Note:
■
When using the RESET TX FIFOS command, the CPU is responsible for releasing the memory
associated with outstanding packets, or re-enqueuing them. Packet numbers in the completion
FIFO can be read via the FIFO ports register before issuing the command.
■
MMU commands releasing memory (commands 4 and 5) should only be issued if the
corresponding packet number has memory allocated to it.
COMMAND SEQUENCING
A second allocate command (command 1) should not be issued until the present one has completed.
Completion is determined by reading the FAILED bit of the allocation result register or through the
allocation interrupt.
A second release command (commands 4, 5) should not be issued if the previous one is still being
processed. The BUSY bit indicates that a release command is in progress. After issuing command 5,
the contents of the PNR should not be changed until BUSY goes low. After issuing command 4,
command 3 should not be issued until BUSY goes low.
BUSY BIT - Readable at bit 0 of the MMU command register address. When set indicates that MMU
is still processing a release command. When clear, MMU has already completed last release
command. BUSY and FAILED bits are set upon the trailing edge of command.
8.17
Bank 2 - Packet Number Register
OFFSET
2
NAME
TYPE
SYMBOL
PNR
PACKET NUMBER
REGISTER
READ/WRITE
Reserved
0
Reserved
0
PACKET NUMBER AT TX AREA
0
0
0
0
0
0
PACKET NUMBER AT TX AREA - The value written into this register determines which packet number
is accessible through the TX area. Some MMU commands use the number stored in this register as
the packet number parameter. This register is cleared by a RESET or a RESET MMU Command.
OFFSET
3
NAME
TYPE
SYMBOL
ARR
ALLOCATION RESULT
REGISTER
READ ONLY
This register is updated upon an ALLOCATE MEMORY MMU command.
SMSC LAN91C111-REV B
Revision 1.8 (07-13-05)
DATA6S9HEET
SMSC [ SMSC CORPORATION ]
