High Performance Single-Chip 10/100 Non-PCI Ethernet Controller
Datasheet
5.3.12
TX_FIFO_INF—Transmit FIFO Information Register
Offset:
80h
Size:
32 bits
This register contains the free space in the transmit data FIFO and the used space in the transmit
status FIFO in the LAN9118.
BITS
31-24
23-16
DESCRIPTION
Reserved
TYPE
RO
DEFAULT
-
TX Status FIFO Used Space (TXSUSED). Indicates the amount of space
in DWORDS used in the TX Status FIFO.
RO
00h
15-0
TX Data FIFO Free Space (TDFREE). Reads the amount of space in bytes,
available in the TX data FIFO. The application should never write more data
than is available, as indicated by this value.
RO
1200h
5.3.13
PMT_CTRL— Power Management Control Register
Offset:
84h
Size:
32 bits
This register controls the Power Management features. This register can be read while the
LAN9118 is in a power saving mode.
Note: The LAN9118 must always be read at least once after power-up, reset, or upon return from a
power-saving state or write operations will not function.
BITS
DESCRIPTION
RESERVED
TYPE
DEFAULT
31:14
13-12
RO
SC
-
Power Management Mode (PM_MODE) – These bits set the LAN9118 into
the appropriate Power Management mode. Special care must be taken when
modifying these bits.
00b
Encoding:
00b – D0 (normal operation)
01b – D1 (wake-up frame and magic packet detection are enabled)
10b – D2 (can perform energy detect)
11b – RESERVED - Do not set in this mode
Note:
When the LAN9118 is in a any of the reduced power modes, a write
of any data to the BYTE_TEST register will wake-up the device. DO
NOT PERFORM WRITES TO OTHER ADDRRESSES while the
READY bit in this register is cleared.
11
10
RESERVED
RO
SC
-
PHY Reset (PHY_RST) – Writing a ‘1’ to this bit resets the PHY. The internal
logic automatically holds the PHY reset for a minimum of 100us. When the
PHY is released from reset, this bit is automatically cleared. All writes to this
bit are ignored while this bit is high.
0b
Revision 1.3 (05-31-07)
SMSC LAN9118
DATA8S2HEET
SMSC [ SMSC CORPORATION ]
