High Performance Single-Chip 10/100 Non-PCI Ethernet Controller
Datasheet
Table 5.3 Valid TX/RX FIFO Allocations (continued)
TX DATA FIFO
SIZE (BYTES)
TX STATUS FIFO
SIZE (BYTES)
RX DATA FIFO
SIZE (BYTES)
RX STATUS FIFO
SIZE (BYTES)
TX_FIF_SZ
4
5
3584
4608
512
512
512
512
512
512
512
512
512
512
512
11520
10560
9600
8640
7680
6720
5760
4800
3840
2880
1920
768
704
640
576
512
448
384
320
256
192
128
6
5632
7
6656
8
7680
9
8704
10
11
12
13
14
9728
10752
11776
12800
13824
In addition to the host-accessible FIFOs, the MAC Interface Layer (MIL) contains an additional 2K
bytes of TX, and 128 bytes of RX FIFO buffering. These sizes are fixed, and cannot be adjusted by
the host.
As space in the TX MIL (Mac Interface Layer) FIFO frees, data is moved into it from the TX data FIFO.
Depending on the size of the frames to be transmitted, the MIL can hold up to two Ethernet frames.
This is in addition to any TX data that may be queued in the TX data FIFO.
Conversely, as data is received by the LAN9118, it is moved from the MAC to the RX MIL FIFO, and
then into the RX data FIFO. When the RX data FIFO fills up, data will continue to collect in the RX
MIL FIFO. If the RX MIL FIFO fills up and overruns, subsequent RX frames will be lost until room is
made in the RX data FIFO. For each frame of data that is lost, the RX Dropped Frames Counter
(RX_DROP) is incremented.
RX and TX MIL FIFO levels are not visible to the host processor. RX and TX MIL FIFOs operate
independent of the TX adatand RX data and status FIFOs. FIFO levels set for the RX and TX data
and Status FIFOs do not take into consideration the MIL FIFOs.
Revision 1.3 (05-31-07)
SMSC LAN9118
DATA8S0HEET
SMSC [ SMSC CORPORATION ]
