High Performance Single-Chip 10/100 Non-PCI Ethernet Controller
Datasheet
BITS
DESCRIPTION
TYPE
R/W
DEFAULT
9
Wake-On-Lan Enable (WOL_EN) – When set, the PME signal (if enabled
with PME_EN) will be asserted in accordance with the PME_IND bit upon a
WOL event. When set, the PME_INT will also be asserted upon a WOL
event, regardless of the setting of the PME_EN bit.
0b
8
Energy-Detect Enable (ED_EN) - When set, the PME signal (if enabled with
PME_EN) will be asserted in accordance with the PME_IND bit upon an
Energy-Detect event. When set, the PME_INT will also be asserted upon an
Energy Detect event, regardless of the setting of the PME_EN bit.
R/W
RO
0b
7
6
RESERVED
-
PME Buffer Type (PME_TYPE) – When cleared, enables PME to function
as an open-drain buffer for use in a Wired-Or configuration. When set, the
PME output is a Push-Pull driver. When configured as an open-drain output
the PME_POL field is ignored, and the output is always active low.
R/W
NASR
0b
5-4
WAKE-UP Status (WUPS) – This field indicates the cause of a wake-up
event detection as follows
R/WC
00
00b -- No wake-up event detected
01b -- Energy detected
10b -- Wake-up frame or magic packet detected
11b -- Indicates multiple events occurred
WUPS bits are cleared by writing a ‘1’ to the appropriate bit. The device must
return to the D0 state (READY bit set) before these bits can be cleared.
Note:
In order to clear this bit, it is required that all event sources be
cleared as well. The event sources are decribed in Figure 3.11 PME
and PME_INT Signal Generationon page 40.
3
PME indication (PME_IND). The PME signal can be configured as a pulsed
output or a static signal, which is asserted upon detection of a wake-up
event.
R/W
0b
When set, the PME signal will pulse active for 50mS upon detection of a
wake-up event.
When clear, the PME signal is driven continously upon detection of a wake-
up event.
The PME signal can be deactivated by clearing the WUPS bits, or by
clearing the appropriate enable (refer to Section 3.10.2.3, "Power
Managment Event Indicators," on page 40).
2
PME Polarity (PME_POL). This bit controls the polarity of the PME signal.
When set, the PME output is an active high signal. When reset, it is active
low. When PME is configured as an open-drain output this field is ignored,
and the output is always active low.
R/W
NASR
0b
1
0
PME Enable (PME_EN). When set, this bit enables the external PME signal.
R/W
RO
0b
-
This bit does not affect the PME interrupt (PME_INT).
Device Ready (READY). When set, this bit indicates that LAN9118 is ready
to be accessed. This register can be read when LAN9118 is in any power
management mode. Upon waking from any power management mode,
including power-up, the host processor can interrogate this field as an
indication when LAN9118 has stabilized and is fully alive. Reads and writes
of any other address are invalid until this bit is set.
Note:
With the exception of HW_CFG and PMT_CTRL, read access to
any internal resources is forbidden while the READY bit is cleared.
SMSC LAN9118
Revision 1.3 (05-31-07)
DATA8S3HEET
SMSC [ SMSC CORPORATION ]
