High Performance Single-Chip 10/100 Non-PCI Ethernet Controller
Datasheet
BITS
DESCRIPTION
TYPE
DEFAULT
2
TX Status Allow Overrun (TXSAO). When this bit is cleared, data
transmission is suspended if the TX Status FIFO becomes full. Setting this
bit high allows the transmitter to continue operation with a full TX Status
FIFO.
R/W
0
Note:
This bit does not affect the operation of the TX Status FIFO Full
interrupt.
1
0
Transmitter Enable (TX_ON). When this bit is set (1), the transmitter is
enabled. Any data in the TX FIFO will be sent. This bit is cleared
automatically when STOP_TX is set and the transmitter is halted.
R/W
SC
0
0
Stop Transmitter (STOP_TX). When this bit is set (1), the transmitter will
finish the current frame, and will then stop transmitting. When the transmitter
has stopped this bit will clear. All writes to this bit are ignored while this bit
is high.
5.3.9
HW_CFG—Hardware Configuration Register
Offset:
74h
Size:
32 bits
This register controls the hardware configuration of the LAN9118 Ethernet Controller.
Note: The transmitter and receiver must be stopped before writing to this register. Refer to Section
3.12.9, "Stopping and Starting the Transmitter," on page 52 and Section 3.13.4, "Stopping and
Starting the Receiver," on page 56 for details on stopping the transmitter and receiver.
BITS
31-22
21
DESCRIPTION
Reserved
TYPE
RO
DEFAULT
-
Transmit Threshold Mode (TTM). This bit is used to control the transmit
threshold the MIL uses as shown in the two tables in the TR field of this
register. This bit is ignored when the SF bit is set (1).
R/W
0
This bit should be set to '1' when operating in 10Mbps mode, and cleared
to '0' when operating in 100Mbps mode if the SF bit cleared.
20
Store and Forward (SF). When set, this bit instructs the MIL to store a
frame of transmit data in the MIL buffer before forwarding to its final
destination.
R/W
0
If this bit is set, the MIL buffers the entire frame before transmitting. TTM
and TR (see bits 21,13, and 12) are treated as Don’t Cares once the SF
mode is selected.
If this bit is reset, the MAC initiates transmission before it receives the entire
frame from the HBI (Host Bus Interface). TTM and TR (see bit 21,13, and
12) determine when the MIL initiates the transmission. If the host cannot
keep up with the MAC transmitting the Ethernet Packet, there is a risk of an
Underrun Error.
SMSC LAN9118
Revision 1.3 (05-31-07)
DATA7S7HEET
SMSC [ SMSC CORPORATION ]
