High Performance Single-Chip 10/100 Non-PCI Ethernet Controller
Datasheet
BITS
18
DESCRIPTION
TYPE
R/W
DEFAULT
PHY (PHY_INT_EN)
0
0
17
16
15
14
13
12
11
10
9
Power Management Event Interrupt Enable (PME_INT_EN)
TX Status FIFO Overflow (TXSO_EN)
R/W
R/W
R/W
R/W
R/W
RO
0
Receive Watchdog Time-out Interrupt (RWT_INT_EN)
Receiver Error Interrupt (RXE_INT_EN)
Transmitter Error Interrupt (TXE_INT_EN)
Reserved
0
0
0
-
TX Data FIFO Underrun Interrupt (TDFU_INT_EN)
TX Data FIFO Overrun Interrupt (TDFO_INT_EN)
TX Data FIFO Available Interrupt (TDFA_INT_EN)
TX Status FIFO Full Interrupt (TSFF_INT_EN)
TX Status FIFO Level Interrupt (TSFL_INT_EN)
RX Dropped Frame Interrupt Enable (RXDF_INT_EN)
RX Data FIFO Level Interrupt (RDFL_INT_EN)
RX Status FIFO Full Interrupt (RSFF_INT_EN)
RX Status FIFO Level Interrupt (RSFL_INT_EN)
GPIO [2:0] (GPIOx_INT_EN).
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
8
0
7
0
6
0
5
0
4
0
3
0
2-0
000
5.3.5
BYTE_TEST—Byte Order Test Register
Offset:
64h
Size:
32 bits
This register can be used to determine the byte ordering of the current configuration
BITS
DESCRIPTION
Byte Test
TYPE
DEFAULT
31:0
RO
87654321h
Revision 1.3 (05-31-07)
SMSC LAN9118
DATA7S4HEET
SMSC [ SMSC CORPORATION ]
