High Performance Single-Chip 10/100 Non-PCI Ethernet Controller
Datasheet
Table 5.1 LAN9118 Direct Address Register Map (continued)
CONTROL AND STATUS REGISTERS
BASE ADDRESS
+ OFFSET
SYMBOL
REGISTER NAME
Free Run Counter
DEFAULT
9Ch
A0h
A4h
FREE_RUN
RX_DROP
-
RX Dropped Frames Counter
00000000h
00000000h
MAC_CSR_CMD
MAC CSR Synchronizer Command (MAC
CSR’s are indexed through this register)
A8h
ACh
B0h
MAC_CSR_DATA
AFC_CFG
MAC CSR Synchronizer Data
00000000h
00000000h
00000000h
Automatic Flow Control Configuration
E2P_CMD
EEPROM command (The EEPROM is
indexed through this register)
B4h
E2P_DATA
EEPROM Data
00000000h
-
B8h - FCh
RESERVED
Reserved for future use
5.3.1
ID_REV—Chip ID and Revision
Offset:
50h
Size:
32 bits
This register contains the ID and Revision fields for this design.
BITS
31-16
15-0
DESCRIPTION
TYPE
RO
DEFAULT
0118h
Chip ID. This read-only field identifies this design
Chip Revision. This is the current revision of the chip.
RO
0001h
Revision 1.3 (05-31-07)
SMSC LAN9118
DATA7S0HEET
SMSC [ SMSC CORPORATION ]
