High Performance Single-Chip 10/100 Non-PCI Ethernet Controller
Datasheet
Table 6.1 Read After Write Timing Rules (continued)
MINIMUM WAIT TIME FOR READ
FOLLOWING ANY WRITE CYCLE
(IN NS)
NUMBER OF BYTE_TEST
READS
REGISTER NAME
(ASSUMING TCYCLE OF 45NS)
RX_CFG
TX_CFG
45
45
45
45
0
1
1
1
1
0
3
7
1
1
3
1
4
0
1
1
1
1
1
HW_CFG
RX_DP_CTRL
RX_FIFO_INF
TX_FIFO_INF
PMT_CTRL
GPIO_CFG
GPT_CFG
135
315
45
45
135
45
180
0
GPT_CNT
ENDIAN
FREE_RUN
RX_DROP
MAC_CSR_CMD
MAC_CSR_DATA
AFC_CFG
45
45
45
45
45
E2P_CMD
E2P_DATA
6.1.2
Special Restrictions on Back-to-Back Read Cycles
There are also restrictions on specific back-to-back read operations. These restrictions concern
reading specific registers after reading resources that have side effects. In many cases there is a delay
between reading the LAN9117, and the subsequent indication of the expected change in the control
register values.
In order to prevent the host from reading stale data on back-to-back reads, minimum wait periods have
been established. These periods are specified in Table 6.2, "Read After Read Timing Rules". The host
processor is required to wait the specified period of time between read operations of specific
combinations of resources. The wait period is dependant upon the combination of registers being read.
Performing "dummy" reads of the BYTE_TEST register is a convenient way to guarantee that the
minimum wait time restriction is met. Table 6.2 also shows the number of dummy reads that are
required for back-to-back read operations. The number of BYTE_TEST reads in this table is based on
the minimum timing for Tcycle (45ns). For microprocessors with slower busses the number of reads
may be reduced as long as the total time is equal to, or greater than the time specified in the table.
Dummy reads of the BYTE_TEST register are not required as long as the minimum time period is met.
Revision 1.1 (05-17-05)
116
SMSC LAN9117
DATASHEET
SMSC [ SMSC CORPORATION ]
