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LAN83C185_03 参数 Datasheet PDF下载

LAN83C185_03图片预览
型号: LAN83C185_03
PDF下载: 下载PDF文件 查看货源
内容描述: 高性能单芯片低功耗10/100以太网物理层收发器 [High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver]
分类和应用: 以太网局域网(LAN)标准
文件页数/大小: 65 页 / 888 K
品牌: SMSC [ SMSC CORPORATION ]
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High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver (PHY)  
Datasheet  
Table 4.1 4B/5B Code Table (continued)  
CODE  
RECEIVER  
TRANSMITTER  
GROUP  
SYM  
INTERPRETATION  
INTERPRETATION  
00010  
00011  
00101  
01000  
01100  
10000  
V
V
V
V
V
V
INVALID, RX_ER if during RX_DV  
INVALID, RX_ER if during RX_DV  
INVALID, RX_ER if during RX_DV  
INVALID, RX_ER if during RX_DV  
INVALID, RX_ER if during RX_DV  
INVALID, RX_ER if during RX_DV  
INVALID  
INVALID  
INVALID  
INVALID  
INVALID  
INVALID  
4.2.3  
Scrambling  
Repeated data patterns (especially the IDLE code-group) can have power spectral densities with large  
narrow-band peaks. Scrambling the data helps eliminate these peaks and spread the signal power  
more uniformly over the entire channel bandwidth. This uniform spectral density is required by FCC  
regulations to prevent excessive EMI from being radiated by the physical wiring.  
The seed for the scrambler is generated from the PHY address, PHYAD[4:0], ensuring that in multiple-  
PHY applications, such as repeaters or switches, each PHY will have its own scrambler sequence.  
The scrambler also performs the Parallel In Serial Out conversion (PISO) of the data.  
4.2.4  
4.2.5  
NRZI and MLT3 Encoding  
The scrambler block passes the 5-bit wide parallel data to the NRZI converter where it becomes a  
serial 125MHz NRZI data stream. The NRZI is encoded to MLT-3. MLT3 is a tri-level code where a  
change in the logic level represents a code bit “1” and the logic output remaining at the same level  
represents a code bit “0”.  
100M Transmit Driver  
The MLT3 data is then passed to the analog transmitter, which launches the differential MLT-3 signal,  
on outputs TXP and TXN, to the twisted pair media via a 1:1 ratio isolation transformer. The 10Base-  
T and 100Base-TX signals pass through the same transformer so that common “magnetics” can be  
used for both. The transmitter drives into the 100impedance of the CAT-5 cable. Cable termination  
and impedance matching require external components.  
4.2.6  
100M Phase Lock Loop (PLL)  
The 100M PLL locks onto reference clock and generates the 125MHz clock used to drive the 125 MHz  
logic and the 100Base-Tx Transmitter.  
SMSC LAN83C185  
Rev. 0.6 (12-12-03)  
DATA1S3HEET