Control Registers, Bank 2
CONTROL REGISTER 1
Default is 0; cleared upon Vbat POR. This
register is battery backed-up.
Bank 2 of the RTC has one control register.
D7
0
D6
0
D5
0
D4
0
D3
0
D2
VTR_POR
_EN
D1
0
D0
AL2_REM
_EN
Frequency Divider
BIT 0 - AL2_REM_EN
The RTC has 22 binary divider stages following
the clock input. The output of the divider is a 1
Hz signal to the update-cycle logic. The divider
is controlled by the three divider bits (DV3-DV0)
in Register A. As shown in Table 70 the divider
control bits can select the operating mode, or
be used to hold the divider chain reset which
allows precision setting of the time. When the
divider chain is changed from reset to the
operating mode, the first update cycle is
one-half second
One of the two control bits for the alarm 2
wakeup function; it is the “remember” enable bit
for the second alarm. This bit, if set to 1, will
cause the system to power-up upon return of
power if the alarm 2 time has passed during
loss of power. It is only applicable when
VTR=0. This bit is independent of the other
control bit for the alarm 2 wake-up function,
Al2_EN (bit 4 of the Soft Power Enable Register
2) which controls alarm 2 when VTR=5V. See
the alarm
information.
2
function section for more
The function of Bit is
later. The divider control bits are also used to
facilitate testing of the RTC.
0
summarized as follows:
Periodic Interrupt Selection
If AL2_REM_EN is set and VTR=0 at the
date/time that alarm 2 is set for, the nPowerOn
pin will go active (low) and the machine will
power-up as soon as VTR comes back.
The periodic interrupt allows the IRQB port to be
triggered from once every 500 ms to once every
122.07 ms. As Table 71 shows, the periodic
interrupt is selected with the RS0-RS3 bits in
Register A. The periodic interrupt is enabled
with the PIE bit in Register B.
BIT 2 - VTR_POR
The enable bit for VTR POR. If VTR_POR_EN
is set, the nPowerOn pin will go active (low) and
the machine will power-up as soon as a VTR
POR occurs.
157
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