GPI/O registers GP1 through GP7, as well as
the Soft Power and SMI Enable and Status
registers, can be accessed by the host when the
chip is in the normal run mode if CR03 Bit[7]=1.
The host uses an index and data register to
access these registers. The Power on default
index and data registers are 0xEA and 0xEB
respectively. In configuration mode the index
address may be programmed to reside on
addresses 0xE0, 0xE2, 0xE4 or 0xEA. The Data
address is automatically set to the index
address + 1. Upon exiting the configuration
mode, the new index and data registers are
used to access registers GP1 through GP7 and
Soft Power and SMI Enable and Status
Registers.
To access the GP1 register when in normal
(run) mode, the host should perform an IOW of
0x01 to the index register (at 0xEX) to select
GP1 and then read or write the data register (at
Index+1) to access the GP1 register. To access
GP2 the host should perform an IOW of 0x02 to
the index register and then access GP2 through
the data register. GP4-7 and the soft power and
SMI
registers
are
accessed
similarly.
Additionally the host can access the
WDT_CTRL (Watch Dog Timer Control)
Configuration Register while in the normal (run)
mode by writing an 0x03 to the index register.
The GP registers can also be accessed by the
host when in configuration mode through CRF6-
FB of Logical Device 8.
Table 51A - Index and Data Register
REGISTER
Index
ADDRESS
NORMAL (RUN) MODE
0xE0, E2, E4, EA
Index address + 1
0x01-0x0F
Data
Access to GP1, GP2,
Watchdog Timer Control,
GP4, GP5, GP6, GP7, Soft
Power and SMI Enable and
Status Registers (see
Table 51B)
122
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