The LOCK command defines whether the EFIFO, FIFOTHR, and PRETRK parameters of the CONFIGURE
command can be RESET by the DOR and DSR registers. When the LOCK bit is set to logic “1” all subsequent
“software RESETS by the DOR and DSR registers will not change the previously set parameters to their default
values. All “hardware” RESET from the RESET pin will set the LOCK bit to logic “0” and return the EFIFO,
FIFOTHR, and PRETRK to their default values. A status byte is returned immediately after issuing a LOCK
command. This byte reflects the value of the LOCK bit set by the command byte.
ENHANCED DUMPREG
The DUMPREG command is designed to support system run-time diagnostics and application software development
and debug. To accommodate the LOCK command and the enhanced PERPENDICULAR MODE command the
eighth byte of the DUMPREG command has been modified to contain the additional data from these two commands.
Compatibility
The FDC37N3869 was designed with software compatibility in mind. It is a fully backwards-compatible solution with
the older generation 765A/B disk controllers. The FDC also implements on-board registers for compatibility with the
PS/2, as well as PC/AT and PC/XT, floppy disk controller subsystems. After a hardware reset of the FDC, all
registers, functions and enhancements default to a PC/AT, PS/2 or PS/2 Model 30 compatible operating mode,
depending on how the IDENT and MFM bits are configured by the system BIOS.
Parallel Port Floppy Disk Controller
In this mode, the Floppy Disk Control signals are available on the parallel port pins. When this mode is selected, the
parallel port is not available. There are two modes of operation, PPFD1 and PPFD2. These modes can be selected
in Configuration Register 4. PPFD1 has only drive 1 on the parallel port pins; PPFD2 has drive 0 and 1 on the
parallel port pins.
PPFD1: Drive 0 is on the FDC pins
Drive 1 is on the Parallel port pins
PPFD2: Drive 0 is on the Parallel port pins
Drive 1 is on the Parallel port pins
When the PPFDC is selected the following pins are set as follows:
1) nDACK: Assigned to the parallel port device during configuration.
2) PDRQ (assigned to the parallel port): not ECP = high-Z, ECP & dmaEn = 0, ECP & not dmaEn = high-Z
3) IRQ assigned to the parallel port: not active, this is hi-Z or Low depending on settings.
The following parallel port pins are read as follows by a read of the parallel port register:
1) Data Register (read) = last Data Register (write)
2) Control Register are read as “cable not connected” STROBE, AUTOFD and SLC = 0 and nINIT = 1;
3) Status Register reads: nBUSY = 0, PE = 0, SLCT = 0, nACK = 1, nERR = 1.
The following FDC pins are all in the high impedance state when the PPFDC is actually selected by the drive select
register:
1) nWDATA, DENSEL, nHDSEL, nWGATE, nDIR, nSTEP, nDS1, nDS0, nMTRO, nMTR1.
2) If PPFDx is selected, then the parallel port can not be used as a parallel port until “Normal” mode is selected.
The FDC signals are muxed onto the Parallel Port pins as shown in Table 46.
Table 46 - FDC Parallel Port Pins
CONNECTOR
PIN #
CHIP PIN #
SPP MODE PIN DIRECTION
FDC MODE PIN DIRECTION
1
2
3
4
5
6
7
75
69
68
67
66
64
63
nSTB
PD0
PD1
PD2
PD3
PD4
PD5
I/O
I/O
I/O
I/O
I/O
I/O
I/O
(nDS0)
nINDEX
nTRK0
I/(0)1
I
I
I
I
I
nWP
nRDATA
nDSKCHG
SMSC DS – FDC37N3869
Page 54
Rev. 10/25/2000
SMSC [ SMSC CORPORATION ]
