Programmed I/O - Transfers from the FIFO to the Host
In the reverse direction an interrupt occurs when serviceIntr is 0 and readIntrThreshold bytes are available in the
FIFO. If at this time the FIFO is full it can be emptied completely in a single burst, otherwise readIntrThreshold
bytes may be read from the FIFO in a single burst.
readIntrThreshold =(16-<threshold>) data bytes in FIFO
An interrupt is generated when serviceIntr is 0 and the number of bytes in the FIFO is greater than or equal to (16-
<threshold>). (If the threshold = 12, then the interrupt is set whenever there are 4-16 bytes in the FIFO.) The PINT pin
can be used for interrupt-driven systems. The host must respond to the request by reading data from the FIFO. This
process is repeated until the last byte is transferred out of the FIFO. If at this time the FIFO is full, it can be
completely emptied in a single burst, otherwise a minimum of (16-<threshold>) bytes may be read from the FIFO in a
single burst.
Programmed I/O - Transfers from the Host to the FIFO
In the forward direction an interrupt occurs when serviceIntr is 0 and there are writeIntrThreshold or more bytes free in
the FIFO. At this time if the FIFO is empty it can be filled with a single burst before the empty bit needs to be
re-read. Otherwise it may be filled with writeIntrThreshold bytes.
writeIntrThreshold = (16-<threshold>) free bytes in FIFO
An interrupt is generated when serviceIntr is 0 and the number of bytes in the FIFO is less than or equal to
<threshold>. (If the threshold = 12, then the interrupt is set whenever there are 12 or less bytes of data in the FIFO.)
The PINT pin can be used for interrupt-driven systems. The host must respond to the request by writing data to the
FIFO. If at this time the FIFO is empty, it can be completely filled in a single burst, otherwise a minimum of (16-
<threshold>) bytes may be written to the FIFO in a single burst. This process is repeated until the last byte is
transferred into the FIFO.
AUTO POWER MANAGEMENT
Power management is provided for the following FDC37N769 logical devices: Floppy Disk, UART1, UART2 and the
Parallel Port. For each logical device two types of power management are provided; direct powerdown and auto
powerdown.
Direct powerdown is controlled by the powerdown bits in the configuration registers. One bit is provided for each
logical device. Auto powerdown can be enabled for each logical device by setting the Auto Powerdown Enable bits in
the configuration registers. In addition, a chip-level hardware powerdown function has been provided through the
PWRGD pin. Refer to Table 1 and to other descriptions of the PWRGD function, for example section
CONFIGURATION, for more information.
FDC Power Management
Direct FDC power management is controlled by FDC Power (bit 3) of Configuration Register 0 (see section CR00 on
page 98). FDC auto power management is enabled by Floppy Disk Enable (bit 7) in CR7 (see section CR07 on
page 102). An internal timer is activated as soon as auto power management is enabled. During the timer
countdown any operation involving the MSR or the Data Register (FIFO) will re-initialize the timer. In auto powerdown
mode the FDC enters the powerdown state when all of the following conditions have been met:
1. The motor enable pins of the DOR register are inactive (zero).
2. The FDC is idle; MSR=80H and INT = 0 (INT may be high even if MSR = 80H due to polling interrupts).
3. The internal head unload timer has expired.
4. The 10msec auto powerdown timer has lapsed.
Disabling the FDC auto power management cancels the internal timer and prevents any of the above conditions from
re-enabling the powerdown state.
DSR From Powerdown
If DSR powerdown is used when the part is in auto powerdown, the DSR powerdown will override the auto
powerdown. However, when the part is awakened from DSR powerdown, the auto powerdown will once again
become effective.
SMSC DS – FDC37N769
Page 91 of 137
Rev. 02-16-07
DATASHEET
SMSC [ SMSC CORPORATION ]
