PS/2 Interface Mode
When IDENT is low and MFM is high PS/2 Interface mode is selected. This mode supports the PS/2 models
50/60/80 configuration and register set. The DMA bit of the Digital Output Register becomes a “don’t care,” FINTR
and DRQ are always valid, TC and DENSEL become active low.
Model 30 Interface Mode
When both IDENT and MFM are low Model 30 Interface Mode is selected. This mode supports PS/2 Model 30
configuration and register set. The DMA enable bit of the Digital Output Register becomes valid, FINTR and DRQ
can be hi-Z, TC is active high and DENSEL is active low.
Floppy Disk Controller Internal Registers
The Floppy Disk Controller contains eight internal registers that provide the interface between the host
microprocessor and the floppy disk drives.
Table 4 shows the addresses required to access these registers. Registers other than the ones shown are not
supported.
Table 4 - Status, Data and Control Registers
BASE I/O
ADDRESS
REGISTER
+0
+1
+2
+3
+4
+4
+5
+6
+7
+7
R
R
R/W
R/W
R
Status Register A
Status Register B
SRA
SRB
DOR
TDR
MSR
DSR
FIFO
Digital Output Register
Tape Drive Register
Main Status Register
Data Rate Select Register
Data (FIFO)
Reserved
Digital Input Register
Configuration Control Register
W
R/W
R
W
DIR
CCR
STATUS REGISTER A (SRA)
Status Register A (Base Address + 0) monitors the state of the FINTR pin and several disk interface pins in PS/2
interface mode (Table 5) and Model 30 interface mode (Table 6). SRA is read-only and can be accessed at any time
when in these modes. During a read in the PC/AT interface mode the data bus pins D0 - D7 are held in a high
impedance state.
PS/2 Interface Mode
Table 5 - SRA PS/2 Mode
7
6
5
4
3
2
1
0
INT
nDRV2
STEP
nTRK0
HDSEL
nINDX
nWP
DIR
PENDING
RESET
0
N/A
0
N/A
0
N/A
N/A
0
CONDITION
Direction, Bit 0
Active high status indicating the direction of head movement. A logic “1” indicating inward direction, a logic “0”
outward.
nWRITE PROTECT, Bit 1
Active low status of the WRITE PROTECT disk interface input. A logic “0” indicating that the disk is write protected.
The nWRITE PROTECT bit also depends upon the state of the Force Write Protect bits in the Force FDD Status
Change configuration register (see section CR17 on page 107).
nINDEX, Bit 2
Active low status of the INDEX disk interface input.
Head Select, Bit 3
Active high status of the HDSEL disk interface input. A logic “1” selects side 1 and a logic “0” selects side 0.
SMSC DS – FDC37N769
Page 17 of 137
Rev. 02-16-07
DATASHEET
SMSC [ SMSC CORPORATION ]
