Motor Enable 0, Bit 0
Active high status of the MTR0 disk interface output pin. This bit is low after a hardware reset and unaffected by a
software reset.
Motor Enable 1, Bit 1
Active high status of the MTR1 disk interface output pin. This bit is low after a hardware reset and unaffected by a
software reset.
Write Gate, Bit 2
Active high status of the WGATE disk interface output.
Read Data Toggle, Bit 3
Every inactive edge of the RDATA input causes this bit to change state.
Write Data Toggle, Bit 4
Every inactive edge of the WDATA input causes this bit to change state.
Drive Select 0, Bit 5
Reflects the status of the Drive Select 0 bit of the DOR (address 3F2 bit 0). This bit is cleared after a hardware reset,
it is unaffected by a software reset.
Reserved, Bits 6 - 7
Always read as a logic “1”.
PS/2 Model 30 Interface Mode
Table 8 - SRB PS/2 Model 30 Mode
7
6
5
4
3
2
1
0
nDRV2
nDS1
nDS0
WDATA RDATA F/F WGATE
nDS3
nDS2
F/F
F/F
RESET
N/A
1
1
0
0
0
1
1
CONDITION
nDRIVE SELECT 2, Bit 0
Active low status of the DS2 disk interface output.
nDRIVE SELECT 3, Bit 1
Active low status of the DS3 disk interface output.
Write Gate, Bit 2
Active high status of the latched WGATE output signal. This bit is latched by the active going edge of WGATE and is
cleared by the read of the DIR register.
Read Data, Bit 3
Active high status of the latched RDATA output signal. This bit is latched by the inactive going edge of RDATA and is
cleared by the read of the DIR register.
Write Data, Bit 4
Active high status of the latched WDATA output signal. This bit is latched by the inactive going edge of WDATA and
is cleared by the read of the DIR register. This bit is not gated with WGATE.
SMSC DS – FDC37N769
Page 19 of 137
Rev. 02-16-07
DATASHEET
SMSC [ SMSC CORPORATION ]
