Table 53 - Chip Level Registers
DESCRIPTION
REGISTER
ADDRESS
STATE
PowerControl
0x22 R/W Bit[0] FDC Power
Bit[1] Reserved
C
Default = 0x00.
on Vcc POR or
Reset_Drv hardware
signal
Bit[2] Reserved
Bit[3] Parallel Port Power
Bit[4] Serial Port 1 Power
Bit[5] Serial Port 2 Power
Bit[6] Reserved
Bit[7] Reserved (read as 0)
= 0 Power off or disabled
= 1 Power on or enabled
Power Mgmt
0x23 R/W Bit[0] FDC
C
Bit[1] Reserved
Default = 0x00.
on Vcc POR or
Reset_Drv hardware
signal
Bit[2] Reserved
Bit[3] Parallel Port
Bit[4] Serial Port 1
Bit[5] Serial Port 2
Bit[6:7] Reserved (read as 0)
= 0 Intelligent Pwr Mgmt off
= 1 Intelligent Pwr Mgmt on
128
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