Chip Level (Global) Control/Configuration
Registers[0x00-0x2F]
The INDEX PORT is used to select
a
The chip-level (global) registers lie in the
address range [0x00-0x2F]. The design MUST
use all 8 bits of the ADDRESS Port for register
selection. All unimplemented registers and bits
ignore writes and return zero when read.
configuration register in the chip. The DATA
PORT is then used to access the selected
register. These registers are accessable only in
the Configuration Mode.
Table 53 - Chip Level Registers
ADDRESS DESCRIPTION
REGISTER
STATE
Chip (Global) Control Registers
0x00 -
0x01
Reserved - Writes are ignored, reads return 0.
Config Control
0x02 W
The hardware automatically clears this bit after the
write, there is no need for software to clear the bits.
Bit 0 = 1: Soft Reset. Refer to the "Configuration
Registers" table for the soft reset value for each
register.
C
Default = 0x00
on Vcc POR or
Reset_Drv
0x03 - 0x06
Reserved - Writes are ignored, reads return 0.
Logical Device #
0x07 R/W A write to this register selects the current logical
device. This allows access to the control and
configuration registers for each logical device.
Note: the Activate command operates only on the
selected logical device.
C
Default = 0x00
on Vcc POR or
Reset_Drv
Card Level
Reserved
0x08 - 0x1F
Reserved - Writes are ignored, reads return 0.
Chip Level, SMSC Defined
Device ID
0x20 R
A
read only register which provides device
C
C
identification. Bits[7:0] = 0x47 when read.
Hard wired
= 0x47
Device Rev
0x21 R
A read only register which provides device revision
information. Bits[7:0] = 0x00 when read.
Hard wired
= Current Revision
127
SMSC [ SMSC CORPORATION ]
