Notes: 1. HARD RESET: RESET_DRV pin asserted
2. SOFT RESET: Bit 0 of Configuration Control register set to one
3. All host accesses are blocked for 500µs after Vcc POR (see Power-up Timing Diagram)
Table 52 - Configuration Registers
Vcc
POR RESET
GLOBAL CONFIGURATION REGISTERS
SOFT
INDEX
TYPE
HARD RESET
CONFIGURATION REGISTER
0x02
0x07
0x20
0x21
0x22
0x23
0x24
0x26
W
0x00
0x00
-
-
-
Config Control
R/W
R
0x00 Logical Device Number
Device ID - hard wired
0x47
Current Revision
R
Device Rev - hard wired
0x00 Power Control
R/W
R/W
R/W
R/W
0x00
-
-
-
-
0x00
0x04
-
-
-
Power Mgmt
OSC
Sysopt=0: 0xF0
Sysopt=1: 0x70
Sysopt=0: 0x03
Sysopt=1: 0x03
Configuration Port Address Byte 0
0x27
R/W
-
-
Configuration Port Address Byte 1
0x2B
0x2C
0x2D
0x2E
0x2F
R/W
R/W
R/W
R/W
R/W
-
-
-
-
-
0x00
0x00
0x00
0x00
0x00
-
-
-
-
-
TEST 4
TEST 5
TEST 1
TEST 2
TEST 3
LOGICAL DEVICE 0 CONFIGURATION REGISTERS (FDD)
0x30
R/W
R/W
0x00
-
-
0x00 Activate
0x03,0
xF0
0x60,
0x61
0x03,
0xF0
Primary Base I/O Address
0x70
0x74
0xF0
0xF1
0xF2
0xF4
0xF5
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0x06
0x02
0x0E
0x00
0xFF
0x00
0x00
-
-
-
-
-
-
-
0x06 Primary Interrupt Select
0x02 DMA Channel Select
-
-
-
-
-
FDD Mode Register
FDD Option Register
FDD Type Register
FDD0
FDD1
124
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