are always possible with standard or PS/2 mode
using program control of the control signals.
b.
(1)
When
is 0, dmaEn
serviceIntr
is 0, direction is 1 and there
are readIntrThreshold or more
bytes in the FIFO. Also, an
interrupt is generated when
Interrupts
The interrupts are enabled by
in the
serviceIntr
is cleared to 0
serviceIntr
register.
whenever
there
are
ecr
readIntrThreshold or more
bytes in the FIFO.
= 1 Disables the DMA and all of
the service interrupts.
serviceIntr
serviceIntr
3. When nErrIntrEn is 0 and nFault transitions
from high to low or when nErrIntrEn is set
from 1 to 0 and nFault is asserted.
= 0 Enables the selected interrupt
condition. If the interrupting
condition is valid, then the
interrupt
is
generated
4. When ackIntEn is 1 and the nAck signal
transitions from a low to a high.
immediately when this bit is
changed from a 1 to a 0. This
can occur during Programmed
I/O if the number of bytes
removed or added from/to the
FIFO does not cross the
threshold.
FIFO Operation
The FIFO threshold is set in the chip
configuration registers. All data transfers to or
from the parallel port can proceed in DMA or
Programmed I/O (non-DMA) mode as indicated
by the selected mode. The FIFO is used by
selecting the Parallel Port FIFO mode or ECP
Parallel Port Mode. (FIFO test mode will be
addressed separately). After a reset, the FIFO
is disabled. Each data byte is transferred by a
Programmed I/O cycle or PDRQ depending on
the selection of DMA or Programmed I/O mode.
The interrupt generated is ISA friendly in that it
must pulse the interrupt line low, allowing for
interrupt sharing. After
following the interrupt event, the interrupt line is
tri-stated so that other interrupts may assert.
a brief pulse low
An interrupt is generated when:
1. For DMA transfers: When
is 0,
The following paragraphs detail the operation of
the FIFO flow control. In these descriptions,
serviceIntr
dmaEn is 1 and the DMA TC is received.
<threshold> ranges from
1
to 16.
The
2. For Programmed I/O:
parameter FIFOTHR, which the user programs,
is one less and ranges from 0 to 15.
a.
When
serviceIntr
direction is
is 0, dmaEn is 0,
and there are
0
writeIntrThreshold or more free bytes in
A low threshold value (i.e. 2) results in longer
periods of time between service requests, but
requires faster servicing of the request for both
read and write cases. The host must be very
responsive to the service request. This is the
desired case for use with a "fast" system.
the FIFO.
generated when
Also, an interrupt is
is cleared
serviceIntr
there
to
0
whenever
are
writeIntrThreshold or more free bytes in
the FIFO.
106
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