AUTO POWER MANAGEMENT
Power management capabilities are provided for
An internal timer is initiated as soon as the auto
powerdown command is enabled. The part is
then powered down when all the conditions are
met. During the countdown of the powerdown
timer, any operation of read MSR or read/write
data (FIFO) will reinitiate the timer.
the following logical devices: floppy disk, UART
1, UART 2 and the parallel port. For each
logical device, two types of power management
are provided; direct powerdown and auto
powerdown.
Direct powerdown is controlled by the
powerdown bits in the configuration registers.
One bit is provided for each logical device. Auto
Powerdown can be enabled for each logical
device by setting the Auto Powerdown Enable
bit in the configluration registers. In addition, a
chip powerdown has been provided by using the
POWERGOOD pin. Refer to the description of
the POWERGOOD pin for more information.
Disabling the auto powerdown mode cancels the
timer and holds the FDC37C669 out of auto
powerdown.
DSR From Powerdown
If DSR powerdown is used when the part is in
auto powerdown, the DSR powerdown will
override the auto powerdown. However, when
the part is awakened from DSR powerdown, the
auto powerdown will once again become
effective.
FDC Power Management
Direct power management is controlled by bit 3
of Configuration Register 0(CR0).
CR0 bit 3 for more information.
Refer to
Wake Up From Auto Powerdown
If the part enters the powerdown state through
the auto powerdown mode, then the part can be
awakened by reset or by appropriate access to
certain registers.
Auto Power Management is enabled by CR7 bit
7. When set, this bit allows FDC to enter
powerdown when all of the following conditions
have been met:
If a hardware or software reset is used then the
part will go through the normal reset sequence.
If the access is through the selected registers,
then the FDC37C669 resumes operation as
though it was never in powerdown. Besides
activating the RESET pin or one of the software
reset bits in the DOR or DSR, the following
register accesses will wake up the part:
1. The motor enable pins of register DOR
(3F2H/372H) are inactive (zero).
2. The part must be idle; MSR=80H and INT =
0 (INT may be high even if MSR = 80H due
to polling interrupts).
3. The internal head unload timer must have
expired.
4. The Auto powerdown timer (10msec) must
have timed out.
1. Enabling any one of the motor enable bits
in the DOR register (reading the DOR does
not awaken the part).
2. A read from the MSR register.
3. A read or write to the Data register.
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SMSC [ SMSC CORPORATION ]
