A high value of threshold (i.e. 12) is used with a
"sluggish" system by affording a long latency
period after a service request, but results in
more frequent service requests.
Restarting the DMA is accomplished by enabling
DMA in the host, setting dmaEn to 1, followed
by setting serviceIntr to 0.
DMA Mode - Transfers from the FIFO to the
Host
DMA TRANSFERS
Note:
- Currently selected Parallel Port
(Note: In the reverse mode, the peripheral may
not continue to fill the FIFO if it runs out of data
to transfer, even if the chip continues to request
more data from the peripheral.)
PDRQ
DRQ channel
- Currently selected Parallel
nPDACK
Port DACK channel
- Currently selected Parallel
PINTR
Port IRQ channel
he ECP activates the PDRQ pin whenever
there is data in the FIFO. The DMA controller
must respond to the request by reading data
from the FIFO. The ECP will deactivate the
PDRQ pin when the FIFO becomes empty or
when the TC becomes true (qualified by
nPDACK), indicating that no more data is
required. PDRQ goes inactive after nPDACK
goes active for the last byte of a data transfer
(or on the active edge of nIOR, on the last byte,
if no edge is present on nPDACK). If PDRQ
goes inactive due to the FIFO going empty, then
PDRQ is active again as soon as there is one
byte in the FIFO. If PDRQ goes inactive due to
the TC, then PDRQ is active again when there
DMA transfers are always to or from the
ecpDFifo, tFifo or CFifo. DMA utilizes the
standard PC DMA services. To use the DMA
transfers, the host first sets up the direction and
state as in the programmed I/O case. Then it
programs the DMA controller in the host with the
desired count and memory address. Lastly it
sets dmaEn to 1 and
to 0. The ECP
serviceIntr
requests DMA transfers from the host by
activating the PDRQ pin. The DMA will empty
or fill the FIFO using the appropriate direction
and mode. When the terminal count in the DMA
controller is reached, an interrupt is generated
and serviceIntr is asserted, disabling DMA. In
order to prevent possible blocking of refresh
requests dReq shall not be asserted for more
than 32 DMA cycles in a row. The FIFO is
enabled directly by asserting nPDACK and
is one byte in the FIFO, and
has
serviceIntr
been re-enabled. (Note: A data underrun may
occur if PDRQ is not removed in time to prevent
an unwanted cycle.)
addresses need not be valid.
PINTR is
Programmed I/O Mode or Non-DMA Mode
generated when a TC is received. PDRQ must
not be asserted for more than 32 DMA cycles in
a row. After the 32nd cycle, PDRQ must be
kept unasserted until nPDACK is deasserted for
a minimum of 350nsec. (Note: The only way to
properly terminate DMA transfers is with a TC).
The ECP or parallel port FIFOs may also be
operated using interrupt driven programmed I/O.
Software can determine the writeIntrThreshold,
readIntrThreshold, and FIFO depth by accessing
the FIFO in Test Mode.
DMA may be disabled in the middle of a transfer
by first disabling the host DMA controller. Then
setting serviceIntr to 1, followed by setting
dmaEn to 0, and waiting for the FIFO to become
empty or full.
Programmed I/O transfers are to the ecpDFifo
at 400H and ecpAFifo at 000H or from the
ecpDFifo located at 400H, or to/from the tFifo at
400H. To use the programmed I/O transfers,
the host first sets up the direction and state, sets
dmaEn to 0 and
to 0.
serviceIntr
107
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