Data bytes are always read from the head of
tFIFO regardless of the value of the direction bit.
For example if 44h, 33h, 22h is written to the
FIFO, then reading the tFIFO will return 44h,
33h, 22h in the same order as was written.
0: Enables an interrupt pulse on the high to
low edge of nFault. Note that an interrupt
will be generated if nFault is asserted
(interrupting) and this bit is written from a 1
to a 0. This prevents interrupts from being
lost in the time between the read of the ecr
and the write of the ecr.
cnfgA (Configuration Register A)
ADDRESS OFFSET = 400H
Mode = 111
BIT 3 dmaEn
Read/Write
This register is a read only register. When read,
10H is returned. This indicates to the system
that this is an 8-bit implementation. (PWord = 1
byte)
1: Enables DMA (DMA starts when serviceIntr
is 0).
0: Disables DMA unconditionally.
BIT 2 serviceIntr
Read/Write
cnfgB (Configuration Register B)
ADDRESS OFFSET = 401H
Mode = 111
1: Disables DMA and all of the service
interrupts.
0: Enables one of the following 3 cases of
interrupts. Once one of the
3 service
BIT 7 compress
This bit is read only. During a read it is a low
level. This means that this chip does not
support hardware RLE compression. It does
support hardware de-compression!
interrupts has occurred serviceIntr bit shall
be set to a 1 by hardware, it must be reset
to 0 to re-enable the interrupts. Writing this
bit to a 1 will not cause an interrupt.
case dmaEn=1:
During DMA (this bit is set to a 1 when
terminal count is reached).
BIT 6 intrValue
Returns the value on the ISA iRq line to
determine possible conflicts.
case dmaEn=0 direction=0:
This bit shall be set to 1 whenever there are
writeIntrThreshold or more bytes free in the
FIFO.
BITS 5:0 Reserved
During a read are a low level. These bits cannot
be written.
case dmaEn=0 direction=1:
This bit shall be set to 1 whenever there are
readIntrThreshold or more valid bytes to be
read from the FIFO.
ecr (Extended Control Register)
ADDRESS OFFSET = 402H
Mode = all
BIT 1 full
This register controls the extended ECP parallel
port functions.
Read only
1: The FIFO cannot accept another byte or the
FIFO is completely full.
BITS 7,6,5
0: The FIFO has at least 1 free byte.
These bits are Read/Write and select the Mode.
BIT 0 empty
BIT 4 nErrIntrEn
Read only
Read/Write (Valid only in ECP Mode)
1: Disables the interrupt generated on the
asserting edge of nFault.
1: The FIFO is completely empty.
0: The FIFO contains at least 1 byte of data.
102
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