NAME
IRQ Mux Control
Register
REG INDEX
0XC0 R/W
DEFINITION
This register is used to configure the IRQs, including PME,
SCI and SMI.
STATE
Default = 0x00
on Vbat POR
Bit[0] Serial/Parallel IRQs
0=Serial IRQs are used
1=Parallel IRQS are used
Note 1: This bit does not control the RTC IRQ, SCI or SMI
interrupts. See bits 1,2,7 of this register.
Note 2: If set, the BIOS buffer is disabled. Also, the
SER_IRQ and PCI_CLK pins are disabled, and these pins
function as IRQ15 and IRQ14, respectively.
Note 3: Select IRQ9 below. Select RTC IRQ and SCI
below. Select nSMI through the SMI register.
Bit[1] RTC IRQ Select.
0=RTC IRQ on serial IRQ frame
1=RTC IRQ on IRQx pin
Bit[2] SCI Select
0=SCI is on serial IRQ frame
1=SCI is on IRQx pin
Note: Serial IRQs are not available under VTR power.
Bit[3] SCI Polarity Select (EN1)
0=SCI active low
1=SCI active high
Bit[4] SCI Buffer Type (EN1)
0=Push-pull
1=Open drain
Bit[6:5] SCI/PME/IRQ9 Pin select
00=Pin 21 is used for nPME signal.
01=Pin 21 is used for SCI.
10=Pin 21 is used for IRQ9.
11=Reserved
Engineering Note: If bit 5 is set, this overrides the setting
of the IRQ for SCI in Config Register 0x70 of Logical
Device A. See the logic in the SCI section.
Enginreering Note: This bit selects the buffer type of the
pin as follows: if nPME is selected, it is active low OD; if
SCI is selected, the buffer type and polarity are selected
through bits 3 and 4 of this register; if IRQ9 is selected, it
is an active high push-pull output.
Bit[7] SMI Select
0=SMI is on serial IRQ frame (IRQ2)
1=SMI is on nSMI pin
Engineering Note: the polarity and buffer type of the SMI
pin is selected through the GPIO registers (default is active
low open drain).
198
SMSC [ SMSC CORPORATION ]
